Your design challenges involve much more than a point-tool solution. That's why Cadence works on solutions for your most challenging problems at a sub-system or system level. You can benefit from the work we've done by exploring the sections below.
3D-IC Design
Enabling maximum functionality in a small form factor
Advanced Node
Proven design flows at 10nm and below
Automotive Solution
Making cars safer and more reliable
Low Power
Every step of the design flow optimized for power
Mixed Signal
Comprehensive, interoperable, and proven verification and implementation
Photonics
Integrated design automation environment
ARM-Based Solutions
Making whole systems possible
Aerospace and Defense
Helping you achieve first-pass success
Press Releases (31)
- Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX™ Process Technology
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Delivers Design and Analysis Flow Enhancements for TSMC InFO and CoWoS® 3D Packaging Technologies
- Cadence Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU
- Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM
- Nagoya University and Cadence Collaborate to Port AUTOSAR-Compliant TOPPERS Automotive Kernel to Tensilica Processors and DSPs
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
- Cadence Expands Online Tool Access for ARM DesignStart Customers to Accelerate SoC Design Delivery
- Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
- Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes
- Cadence Delivers Industry’s First Comprehensive TCL1 Documentation to Support Automotive ISO 26262 Standard
- Cadence Enables Accelerated Implementation and Signoff of New ARM Cortex-M23 and Cortex-M33 Processors
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- Cadence Delivers Integrated System Design Solution for TSMC InFO Packaging Technology
- Cadence Delivers Rapid Adoption Kit for Fast Implementation and Signoff of New ARM Cortex-R52 CPU
- Cadence Expands Collaboration with ARM to Accelerate Custom SoC and IoT System Designs with Industry’s First End-to-End Hosted Design Solution
- Cadence Delivers Rapid Adoption Kits Based on a 10nm Reference Flow for New ARM Cortex-A73 CPU and ARM Mali-G71 GPU
- Cypress Adopts Cadence Digital Implementation and Circuit Simulation Tools for 40nm Automotive Designs
- Tezzaron Cuts Design Time in Half with Cadence Full-Flow Digital RTL-to-Signoff Solution
- Cadence Digital and Signoff Tools Certified on Samsung Foundry's 14LPP Process
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
- Cadence Receives Customers' Choice Award for Automotive IP Paper Presented at TSMC OIP Ecosystem Forum
- Cadence and ARM Deliver an IP Reference System for Internet of Things Applications
- Cadence Announces Verification IP for ARM AMBA 5 AHB5
- Cadence Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 22FDX Platform Reference Flow
- Cadence and ARM Announce Strategic IP Interoperability Agreement
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- Cadence Expands ARM-based System Verification Solution, Reducing Time-to-Market for Mobile, Networking and Server Applications
Webinar (6)
- Meeting ADAS SoC Safety Design Challenges with Active Safety Features Built into IP
- Addressing Smart Sensor Design Challenges for SoCs and IoT Webinar (IoT Webinar Series - Part 2)
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- 5 Steps to Your First Power Shut-off (PSO) Verification
- Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)
- Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)
Demo (3)
White Paper (11)
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- DO-254 Explained White Paper
- Plan-Based Analog Verification Methodology White Paper
- Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper
- Enabling ISO 26262 Qualification By Using Cadence Tools White Paper
- A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper
- Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design White Paper
- Techniques to Accelerate Power and Timing Signoff of Advanced-Node SoCs White Paper
- Solutions for Mixed-Signal SoC Verification Using Real Number Models White Paper
- Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components White Paper
- Solutions for Mixed-Signal SoC Verification White Paper
Success Story Video (4)
- Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- Improving Performance of SoCs with Interconnect Workbench and CoreLink System IP
Product Overview (3)
Datasheet (1)
Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.
Narenda Konda, Director of Engineering, NVIDIA
Processors for automotive and industrial markets are driving higher levels of integration and complexity. This requires larger design partitions to deliver the efficiencies and time to market demanded by our customers.
Anthony Hill, Director of Processor Technology, Texas Instruments
Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.
Martin Kejhar, Senior Technical Staff Engineer and Scientist, ON Semiconductor