Your design challenges involve much more than a point-tool solution. That's why Cadence works on solutions for your most challenging problems at a sub-system or system level. You can benefit from the work we've done by exploring the sections below.
3D-IC Design
Enabling maximum functionality in a small form factor
Advanced Node
Proven design flows at 10nm and below
Aerospace and Defense
Helping you achieve first-pass success
Arm-Based Solutions
Making whole systems possible
Automotive Solutions
Making cars safer and more reliable
Cadence Cloud
The future of electronic design
FPGA Development
Comprehensive Flow for Complex FPGAs
Low Power
Every step of the design flow optimized for power
Machine Learning
Enabling faster, smarter design solutions and product differentiation
Mixed Signal
Comprehensive, interoperable, and proven verification and implementation
Photonics
Integrated design automation environment
Resource Library VIEW ALL
Video (168)
- Removing Cloud Security Barrier
- Cloud Data Management
- Infinite and Immediate Cloud Resources
- The Palladium Solution and SoC Emulation for 16nm Automotive Devices at NXP
- Texas Instruments - Highly Scalable Multicore ARM A15 Verification with Specman/e
- From TensorFlow to RTL in Three Months
- Accelerating design-in of Xilinx FPGAs while optimizing PCB layout for cost and performance
- Standalone AI Processor: Tensilica DNA 100 Processor IP for On-Device AI
- Significance of Sparsity in Neural Networks
- Tensilica Neural Network Compiler: Efficiently Deploy Neural Networks
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
- Automotive Sensor Design Enablement
- Tensilica Hardware Safety Kit ISO 26262
- Whiteboard Wednesdays - Introduction to Functional Safety From an IP Supplier
- Introduction to ADAS with a Real-Life Example
- The Truth about Designing for Automotive Functional Safety
- Big FPGA Boards for ASIC Prototyping
- Case Studies for Successful FPGA Based Prototyping
- Hardware Solutions for FPGA-based Prototyping
- Hardware Solutions for FPGA-Based Prototyping
- Emulating a Dual-Port 10G/40G NIC on Palladium and RPP
- Hitachi: Faster Bring Up with Protium Platform
- Bluespec Taps Into Rapid Prototyping Platform for Hybrid Prototyping
- Faster HW/SW Debug, Embedded Software Development and System Validation
- Protium S1 used to prototype a pedestrian detection application.
- Accelerating design-in of Altera FPGAs while optimizing PCB layout for cost and performance
- New Cadence Products Expand the Verification Suite: Xcelium Parallel Simulator and Protium S1 Platform
- Firmware Development and Pre-silicon Verification with FPGA-based Prototyping
- The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes
- Xilinx - Industry Leading Solutions for FPGA-based Prototyping
- FPGA Prototyping Enables Rapid Development of Customizable Processors
- FPGA-Prototyping of an Automotive Ethernet based Parking Assist System
- Reduce FPGA-Based Prototype Bring-Up From Months to Days with Cadence Protium S1 Platform
- Faster Routing by Optimizing FPGA Pin Assignments
- FPGA board design: Introduction to Cadence FPGA System Planner
- Cadence Cloud – The Future of Electronic Design
- Library Characterization in the Cloud
- Faster Timing Characterization of Analog Macros
- Cloud Whiteboard: Why Cloud for EDA
- Cloud Whiteboard: The 4 Values of Cadence Cloud
- Cloud Whiteboard: Cadence Cloud Offerings
- Automotive Ethernet Audio Demo: An Overview
- Renesas R-Car Audio Channel Processing using Cadence Tensilica DSP
- AI for Image Classification and Object Detection
- Full HD 360° Surround View enabled by Tensilica Vision P6 DSP
- AI for People Detection using Tensilica Vision P6 DSP
- Automotive Sensors: Concepts and Trends
- Cadence Automotive – from Concepts to Solutions
- Breaking Down ADAS Sensor Fusion Platforms and Sensor Concepts
- Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
- Hardent: Solution for Next-Generation Automotive Video Systems Enabled with Cadence IP
- A Peek Inside Future Automotive Networks
- Ethernet and Automotive Electronics
- How to Meet the Quality, High Reliability, and Safety Requirements for Analog and Mixed-Signal ICs in Mission-Critical Applications
- Easily Adopt Electro-thermal Simulation for Your High-Reliability Analog Designs
- Automotive System Trends and the Integration of Analog Electronic Dependability
- Analog Defect Simulation and Analysis for Complex Systems
- Improvements in Modeling Device Aging Analysis: Extending Product Lifetime
- How Electronics are Driving the Coolest Features in Today's Cars
- Taking FPGA-Based Prototyping to the Next Level
- Simplifying Fault Injection Simulations for Functional Safety Verification
- A Practical Approach to Failure Modes, Effects, and Diagnostic Analysis (FMEDA)
- Understanding ISO 26262 Implications for Automotive Design Teams
- Automotive Memory Technologies and Trends: Technology Implications
- Summary of Keynote by Davide Santo from NXP on Artificial Intelligence in Autonomous Driving
- Cadence Enables NXP’s Next Generation Radar Sensor
- Low Power Embedded CNN with Tensilica High-Performance Vision DSP
- Active Safety Features
- Automotive Functional Safety and the ISO 26262 Standard
- Analog Behavioral Modeling and Model Generation
- Industry Trends and Requirements for Autonomous Driving
- Radar Signal Processing for Automotive Applications
- Radar Signal Processing Optimized for the Tensilica Fusion G3 DSP
- Modular VIP Architecture
- Memory Trends to Fit Your Application
- Tensilica Vision P6 DSP Enhanced for CNN
- Where Ethernet is Used in Automotive Electronics
- Implementation of Higher Speed PCIe Gen4 IP
- Renesas: Balancing Performance, Low-Power and Functional Safety in ADAS Applications
- Renesas: Next-generation Integrated Cockpits Using Cadence Tensilica HiFi DSPs
- Pedestrian Detection: Cadence Tensilica IVP DSP on Cadence Protium FPGA-based prototyping platform
- Automotive IP Subsystems
- Berthold Hellenthal, Audi, CDNLive EMEA 2014 Keynote
- Cadence virtual hardware in-the-loop environment for ECU design
- Big Automotive Trends and Challenges - Lars Reger, NXP Semiconductors
- lars reger nxp role of semiconductor industry in automotive innovation 1080p
- Lars Reger,NXP, delivers keynote at CDNLive EMEA 2015
- Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow
- Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- 2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor
- Low-Power Mixed-Signal Verification of Freescale Kinetis Products
- Verification Solutions for ARM v7/v8 Based Systems on Chip
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
- Advanced Node Multi-Patterning Technologies within Virtuoso Environment
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- How Real Number Modeling Improves Functional Verification for Mixed-Signal SoCs
- Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon
- Detecting Low-Power Bugs with X-Optimism Simulation
- Detecting System-Level Corner Cases During Low-Power SoC Verification
- Faster HW/SW Verification and Bring-up with Hybrid Virtual Platform
- Cadence Functional Safety Solution
- Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip Level
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- System Level Low Power Verification Using Palladium and CPF
- 5 Steps to Your First Power Shut-off (PSO) Verification
- Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power Solution
- MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium Platform
- Allegro Microsystems Improves Efficiency and Productivity with Incisive vManager Solution
- STMicroelectronics 20nm Constraint Driven Modgen Flow
- Silicon Signoff and Verification - 16nm FinFET Challenges and Features
- Verify Smarter with Industry's First Datacenter-Class Emulation System
- Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System
- Virtuoso Mixed-Signal "SmartPower" Implementation Flow
- Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC
- How Nvidia is Speeding Up Timing Closure of Advanced-Node Application Processors
- Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES
- Cadence Implementation, Signoff and DFM Readiness for Samsung FinFET Nodes
- Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership
- Accurate Low Power verification on a Complex Low Power Design using CLP
- Physical Design Flow Challenges at 28nm on Multi-Million Gate Blocks
- Physical Design Analytics and DFM Enablement for sub-14nm Technology Nodes
- Enabling Cadence Signoff Technologies for 14nm FinFET at Samsung
- Overcoming Patterning-Induced Place-and-Route Challenges at 10nm
- Freeescale Semiconductor - Cadence Low-Power Solution for Kinetis SoC
- ARM AMBA Protocol Overview
- Cadence Functional Safety Solution for Automotive Design
- Cadence EMEA Student Design Contest Winner- Philipp Wehner, Ruhr University Bochum, at CDNLive EMEA
- Evolution of Electronics in Automotive Industry
- Lars Reger, NXP, Future car- from connectivity to autonomous driving
- STMicro Shortens Turnaround Time with Cadence's Mixed-Signal Solutions
- PMC Gains Faster Analog IP Verification with Virtuoso Platform
- PMC - Power Estimation – An Evolving Science
- Design Challenges in Developing Sub-Volt IP Designs for IoT Applications
- Introducing Low-power Verification RAK
- X-FAB Revamps Low-Power Design Flow with CPF
- Cortex®-M0 and Cortex-M0+: Tiny, easy and energy efficient processors for mixed signal applications
- Custom Layout Methodologies with Virtuoso Advanced Node
- TowerJazz AMS Reference Flow
- Is SystemVerilog the Future of Analog Behavioral Modeling
- Embedded World: Enabling Automotive System Design with Allegro Sigrity Tools
- Virtuoso Technology for Advanced Process Nodes
- STMicroelectronics Automates Full Custom Analog Layout Flow Using Constraints
- S3 Group uses Cadence Mixed-Signal Solution for First-Time-Right Silicon
- Virtuoso IPVS for Advanced Node Design
- Cadence DAC 2015 Clio Soft
- Detecting and Fixing Layout-Dependent Effects Using Virtuoso
- Digital 20nm RTL-to-GDSII Methodology
- Cadence and IBM - Custom 20nm Solution Webinar
- Efficient Design Verification and Yield Estimation
- Is SystemVerilog the Future of Analog Behavioral Modeling
- TSMC Europe discusses the importance of 16nm FinFET technology
- TSMC Europe and Cadence discuss mixed-signal trends in Europe
- IBM and Cadence Collaborate to Solve Advanced Node Design Challenges
- Rapid Adoption of Advanced Cadence Design flows Using X-FAB's AMS Reference Kit
- Cadence and GLOBALFOUNDRIES 20nm Reference Flow
- 6 Must Know Tips to Optimize LPDDR and Wide I/O Performance
- Getting a Jumpstart on 20nm - Part 2
- Silicon Labs - Power Mode Verification in Mixed-Signal Chips
- Getting a Jumpstart on 20nm - Part 1
- GLOBALFOUNDRIES - Collaboration Keys to Building Complex PDKs
- Low-Power Summit ARM Sathya Subramanian
- TowerJazz Substrate Noise Enablement
- Building Energy Efficient SoCs with big.LITTLE Technology
White Paper (20)
- Cadence Cloud—The Future of Electronic Design Automation White Paper
- Accelerating SoC Time to Market with Cloud-Based Verification White Paper
- Improving Test Coverage and Eliminating Test Ecapes Using Analog Defect Analysis White Paper
- DO-254 Explained White Paper
- Accelerating DO-254 Approval with Cadence Tools White Paper
- Meeting the Challenges of the 2018 National Defense Strategy White Paper
- Functional Safety Methodologies for Automotive Applications White Paper
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- Plan-Based Analog Verification Methodology White Paper
- Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper
- Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
- Enabling ISO 26262 Qualification By Using Cadence Tools White Paper
- A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper
- Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design White Paper
- Techniques to Accelerate Power and Timing Signoff of Advanced-Node SoCs White Paper
- Solutions for Mixed-Signal SoC Verification Using Real Number Models White Paper
- Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components White Paper
- Building Energy-Efficient ICs from the Ground Up White Paper
- Solutions for Mixed-Signal SoC Verification White Paper
- 20nm Design - How this Advanced Technology Node Will Transform SoCs and EDA White Paper
Webinar (10)
- Protium FPGA-Based Prototyping Platform
- Analog Behavioral Modeling and Model Generation
- Addressing Smart Sensor Design Challenges for SoCs and IoT Webinar (IoT Webinar Series - Part 2)
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- 5 Steps to Your First Power Shut-off (PSO) Verification
- Cortex®-M0 and Cortex-M0+: Tiny, easy and energy efficient processors for mixed signal applications
- Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)
- Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)
- Understanding the What If to Avoid the What Now
- 6 Must Know Tips to Optimize LPDDR and Wide I/O Performance
Press Releases (65)
- Media Alert: Cadence to Showcase Photonics Applications at Photonics Summit and Workshop with Lumerical
- Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
- Cadence Verification Suite Enabled on Arm-Based HPC Datacenters
- Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
- Cadence Recognized with Four 2018 TSMC Partner of the Year Awards
- Cadence Expands its Cloud Portfolio with Delivery of TSMC OIP Virtual Design Environment
- Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
- Cadence Achieves Amazon Web Services Industrial Software Competency Status for Its Cloud-Hosted Design Solution
- Cadence Full-Flow Digital Tool Suite Achieves GLOBALFOUNDRIES 22FDX® Certification
- Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification
- Cadence Full-Flow Digital and Signoff Tools Certified on Samsung Foundry’s 7LPP Process Technology
- Cadence Delivers the First Broad Cloud Portfolio for the Development of Electronic Systems and Semiconductors
- Cadence Collaborates with Amazon Web Services to Deliver Electronic Systems and Semiconductor Design for the Cloud
- Cadence and Microsoft Collaborate to Facilitate Semiconductor and System Design on the Microsoft Azure Cloud Platform
- Cadence Collaborates with Google Cloud to Enable Cloud-Based Development of Electronic Systems and Semiconductors
- Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
- Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs
- Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
- Cadence Boosts Vision and AI Performance with New Tensilica Vision Q6 DSP IP
- Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
- Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX™ Process Technology
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Delivers Design and Analysis Flow Enhancements for TSMC InFO and CoWoS® 3D Packaging Technologies
- Cadence Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU
- Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM
- Nagoya University and Cadence Collaborate to Port AUTOSAR-Compliant TOPPERS Automotive Kernel to Tensilica Processors and DSPs
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
- Cadence Expands Online Tool Access for ARM DesignStart Customers to Accelerate SoC Design Delivery
- Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
- Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes
- Cadence Delivers Industry’s First Comprehensive TCL1 Documentation to Support Automotive ISO 26262 Standard
- Cadence Enables Accelerated Implementation and Signoff of New ARM Cortex-M23 and Cortex-M33 Processors
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- Cadence Delivers Integrated System Design Solution for TSMC InFO Packaging Technology
- Cadence Delivers Rapid Adoption Kit for Fast Implementation and Signoff of New ARM Cortex-R52 CPU
- Cadence Debuts PSpice Web Portal and Ecosystem to Help Designers Address System Level Mixed-Signal Wireless and IoT Challenges
- Cadence Expands Collaboration with ARM to Accelerate Custom SoC and IoT System Designs with Industry’s First End-to-End Hosted Design Solution
- Cadence Delivers Rapid Adoption Kits Based on a 10nm Reference Flow for New ARM Cortex-A73 CPU and ARM Mali-G71 GPU
- Uurmi Fog Removal Software Now Available on Cadence Tensilica Vision DSPs
- Cypress Adopts Cadence Digital Implementation and Circuit Simulation Tools for 40nm Automotive Designs
- Tezzaron Cuts Design Time in Half with Cadence Full-Flow Digital RTL-to-Signoff Solution
- Cadence Announces New Tensilica Vision P6 DSP Targeting Embedded Neural Network Applications
- Cadence Digital and Signoff Tools Certified on Samsung Foundry's 14LPP Process
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Building the Car of the Future Today-Cadence Showcases Automotive Solutions at embedded world 2016
- Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
- Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
- Cadence Receives Customers' Choice Award for Automotive IP Paper Presented at TSMC OIP Ecosystem Forum
- Cadence and ARM Deliver an IP Reference System for Internet of Things Applications
- Cadence Announces Verification IP for ARM AMBA 5 AHB5
- Cadence Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 22FDX Platform Reference Flow
- Media Alert: Cadence to Host Mixed-Signal Technology Summit
- Cadence and ARM Announce Strategic IP Interoperability Agreement
- Cadence Announces Fourth Generation Tensilica HiFi DSP Architecture
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- Müller-BBM Active Noise Control and Sound Design Now Optimized on Cadence Tensilica HiFi Audio/Voice Processors for Automotive Applications
- SPL Vitalizer In-Car Audio Software Now Available on Cadence Tensilica HiFi Audio/Voice DSP Family
- Cadence and QNX Announce New Tensilica HiFi Audio/Voice DSP Application for In-Car Active Noise Control
- CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
- Cadence Expands ARM-based System Verification Solution, Reducing Time-to-Market for Mobile, Networking and Server Applications
- Cadence Announces Sensor Platforms as New Tensilica HiFi Audio Partner for Sensor Fusion and Context Awareness Applications
Datasheet (11)
- Legato Reliability Solution Datasheet
- Perspec System Verifier Datasheet
- Xcelium Parallel Logic Simulation Datasheet
- Protium S1 Single-FPGA Board Datasheet
- Protium S1 FPGA-Based Prototyping Platform Datasheet
- vManager Metric-Driven Signoff Platform Datasheet
- Virtuoso ADE Verifier Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Stratus High-Level Synthesis Datasheet
- Protium FPGA-Based Prototyping Platform Datasheet
- Allegro FPGA System Planner Datasheet
Success Story Video (8)
- Faster Timing Characterization of Analog Macros
- Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow
- Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES
- Improving Performance of SoCs with Interconnect Workbench and CoreLink System IP
- S3 Group uses Cadence Mixed-Signal Solution for First-Time-Right Silicon
Videos
Customers
Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.
Narenda Konda, Director of Engineering, NVIDIA
Processors for automotive and industrial markets are driving higher levels of integration and complexity. This requires larger design partitions to deliver the efficiencies and time to market demanded by our customers.
Anthony Hill, Director of Processor Technology, Texas Instruments
Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.
Martin Kejhar, Senior Technical Staff Engineer and Scientist, ON Semiconductor