Greetings from the Cadence® India Team!

Chip design in India has moved into the big leagues with multinationals, design services companies, product companies, and start-ups in the country growing by the day. Senior semiconductor executives, as well as trade bodies such as NASSCOM, see this as a sunrise industry, with the only impediment being a potential shortfall of quality VLSI-trained talent.

Therefore, for many years, industry, government, and academia have worked together to build the talent pool, with the aim of making India a VLSI design powerhouse in the global semiconductor world.

As a leader in the electronic design automation (EDA) industry, Cadence has been at the heart of this effort, providing its tools to engineering institutes at rates they can afford. Why? Because Cadence is committed to helping our customers by providing them with a pool of engineers experienced in EDA tool use and methodologies.


Talent is essential in a knowledge-intensive sector like electronic design. India produces a large number of electronics and computer science graduate engineers every year. However, while there is no dearth of talent, the challenge is finding “design-aware” engineers who are trained specifically in VLSI design and can ramp up quickly. Simply put, the industry is facing a quality gap with regard to talent.

Getting fresh graduates ramped up quickly to productivity is a key concern across the industry ecosystem. Several companies have already taken these and other steps to give students real-life experience before they graduate, thereby lessening ramp-up time when they enter the industry.

When Cadence established its Indian presence over 20 years ago, we realized early on the need to nurture and develop the country’s talent pool through public-private partnerships at various levels. These include the Cadence University Program, the Cadence Design Contest, and the Cadence VLSI Certification Program.

Cadence University Program

The Cadence University Program has more than 300 institutes across India, including IITs, NITs, and private engineering colleges. This program aims at giving institutes commercial-grade software to provide students with access to best-in-class technology.

It is important to not only focus on the students, but the faculty as well. Cadence’s Faculty Development Program ensures that faculty is conversant with the latest Cadence technologies so that they are equipped to teach better.

Cadence Design Contest

Launched in 2006, the Cadence Design Contest is a flagship initiative of the Cadence University Program. It provides engineering students with an opportunity to showcase their talent in electronic design. This program is open to undergraduate and graduate students. Projects are judged by an expert committee consisting of Cadence and industry experts on criteria including inventiveness, complexity, feasibility, breadth of design, effective tool usage, and presentation.

In 2010, due to the tremendous response from the student community, the Cadence Design Contest was divided into two categories: master’s and bachelor’s. A winner and runner up are selected from each category.

What’s in it for students?
  • Opportunity to showcase their innovation and design talent
  • Chance to meet and interact with industry experts
  • Recognition from industry and academia
  • Participation certificates for finalists
  • Cash prizes
What’s in it for the faculty?
  • Recognition from industry and academia
  • Participation certificates for finalists
  • Cash prizes
Previous winners and runners-up
Year Institute Project Title Category
2013 College of Engineering - Guindy Power and Data Recovery for Cochlear Implant Winner - Bachelor's Category
2013 Indian Institute of Science Low-Power Biomedical Platform Winner - Master's Category
2013 BVBCET Design of Low Drop-Out, High PSRR LDO for RF Applications Runner Up - Bachelor's Category
2013 IIIT Allahabad A Low Power Asynchronous SAR ADC using 180nm CMOS Technology Runner Up - Master's Category
2012 KS Institute of Technology Design and Implementation of Low Power Pipelined FFT Processors Using Self Timed Adders Winner - Bachelor's Category
2012 IIT Bombay Low Power, Low Noise Signal Conditioning Chip with Differential “Resistance to Frequency” Converter for Resistive Bridge Sensors Winner - Master's Category
2012 BITS, Pilani Design of Ultra Low Power, Low Noise Implantable Neural Recording Amplifier For Brain Machine Interface Runner Up - Bachelor's Category
2012 PSG College of Technology Low Power, High Performance ASIC Design for Epileptic Seizure Prediction Runner Up - Master's Category
2011 IIT, Kharagpur Design and Implementation of a High Speed Power Efficient Hybrid Mode Sense Amplifier for SRAM Applications Winner - Bachelor's Category
2011 IIT Bombay Scalable Constant Resistance, Transconductance, Gm/C and their Applications Winner - Master's Category
2011 B.L.D.E.A's CET Bijapur Design and Analog VLSI Implementation of Neural Architecture Runner Up - Bachelor's Category
2011 VIT University An Optimized Architecture to Perform Image Compression and Encryption Simultaneously Using Modified DCT Algorithm Runner Up - Master's Category
2010 IIT Kharagpur Low Power and High Speed Realization of Modified Fast Radon Transform using FFT – IFFT ASIC Winner - Master's Category
2010 VESIT Mumbai Implementation of High Speed Vedic Co-Processor Incorporated With a 32 Bit Processor Executing RISC Instruction Set Architecture Winner - Bachelor's Category
2010 IIT Bombay General Purpose Ultra Energy Efficient Programmable Analog Signal Conditioning IC” Runner Up - Master's Category
2010 Jadavpur University ASIC Chip Development of Inverse Delayed Function Model of Neuron Runner Up - Bachelor's Category
2006 Sri Sant Gajanan Maharaj Institute of Technology, Shegaon Design and Implementation of Low Cost Power Optimised OTA Based FPAA in 0.35um Mixed-Mode CMOS Process Winner
2009 IIT Delhi Design of Low-Power and High-Performance Ternary Content Addressable Memory (TCAM) Winner
2009 BVB College of Engineering, Hubli Control Scheme for 1.8V, 2MHz Buck Converter Using Type II PI Controller Runner Up
2008 IIIT Hyderabad Design of a Low Power Variable-Resolution Flash Type- ADC Winner
2008 VESIT Mumbai Low Power AES Crypto Engine With Resistance to DPA Attacks Runner Up
2007 IIT Kharagpur Design & Implementation Of An On-Chip Single Inductor Triple Output DC-DC Buck Converter Winner
2007 I2IT Pune Reconfigurable Floating Point Unit Runner Up
2006 Sri Sant Gajanan Maharaj Institute of Technology, Shegaon Design and Implementation of Low Cost Power Optimised OTA Based FPAA in 0.35um Mixed-Mode CMOS Process Winner

Cadence VLSI Certification Program

The Cadence VLSI Certification Program is a unique, one-of-a-kind program that bridges the gap between inexperienced engineering students and the industry need for trained design-aware talent.

The program offers:

  • World-class curriculum that enables graduates to be industry ready
  • Access to best-in-class Cadence technologies and ecosystem partners
  • An incremental training approach starting with VLSI basics and building up to industry-relevant skills
  • Access to industry experts who deliver the curriculum
  • More than 200 hours of theory—PLUS labs study—to ensure that students get hands-on experience while reinforcing the basics
  • Tool training and soft skills training
  • Conducted on campus during weekends, to be most convenient for the students
  • Participants are eligible to apply for the prestigious Cadence Internship Program