- Custom IC - Analog - RF Design (8)
- System Design and Verification (6)
- Virtuoso Schematic Editor (5)
- Virtuoso Analog Design Environment (4)
- Virtuoso ADE Product Suite (4)
- Spectre Circuit Simulator (3)
- Flows SDV (3)
- Planning and Management (3)
- Incisive vManager Solution (3)
- Virtuoso ADE Assembler (3)
- Circuit Design (3)
- Circuit Simulation (3)
- Virtuoso ADE Explorer (3)
- Virtuoso ADE Verifier (3)
- Spectre Accelerated Parallel Simulator (3)
- Virtuoso Layout Suite (2)
- Voltus-Fi Custom Power Integrity Solution (2)
- Quantus QRC Extraction (2)
- Tempus Timing Signoff Solution (2)
- Voltus IC Power Integrity Solution (2)
- Power-Aware Verification Methodology (2)
- AMS Designer (2)
- Virtuoso AMS Designer (2)
- Simulation and Testbench Verification (2)
- Incisive Enterprise Simulator (2)
- Virtuoso Variation Option (1)
- Spectre RF Simulation (1)
- Space-Based Router (1)
- RF Design (1)
- Layout Verification (1)
- Digital Design and Signoff (1)
- Block Implementation (1)
- Innovus Implementation System (1)
- Flows (1)
- Virtuoso Layout Suite for Electrically Aware Design (1)
- Conformal Low Power (1)
- Genus Synthesis Solution (1)
- Silicon Signoff (1)
- Incisive Specman Elite (1)
23 Result(s) Found
This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers and describes analog real number modeling (RNM) and h...
This paper presents solutions for mixed-signal verification, mixed-signal block and IC level verification using analog behavioral modeling and combined analog and digital solvers.
TI followed the Cadence Digital Mixed Signal (DMS) methodology and extend the successful MDV verification methodology into the analog and mixed-signal domains.
Virtuoso ADE Verifier presents the verification status in an easy-to-use cockpit inside the Virtuoso tool. Updates to the results or to the specifications are automatically reflected in the cockpit and thu...
Cadence Virtuoso ADE Verifier, an analog specification verification cockpit, is designed to provide the analog verification engineer or architect a global view of the circuit status.
Cadence and United Microelectronics Corporation, a leading global semiconductor foundry, today announced that the Cadence analog/mixed-signal IC design flow has achieved certification for UMC’s 28HPC+ proc...
06 Aug 2019
Cadence custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology
23 Oct 2018
Cadence announced plans to host the Mixed-Signal Tech Summit at hq. The theme of event is Perspectives on Mixed-Signal Design: Transistors, Chips, Systems. Attendees of event have the opportunity to learn ...
21 Oct 2015
Cadence technology enables Silicon Labs to accelerate delivery of energy-efficient Blue Gecko Bluetooth Smart SoCs to the IoT market
24 Feb 2016
Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
Kandou Bus has fully tested and characterized a 28nm high-speed SerDes PHY IP design named that was implemented using the Cadence mixed-signal signoff flow
26 Jan 2016