SimVision Simplifies UVM SystemVerilog Macro Debug

Cadence Webinar 2016: Incisive SimVision Simplifies UVM SystemVerilog Macro Debugging. Hourlong video webinar.

Kishore Karnane from Cadence discusses SimVision Simplifies UVM and SystemVerilog Macro Debug. SimVision is Integrated Multi Language Debug Environment. It seemlessly moves between HDL, Testbench domains and cross languages. Design complexity has interactive debug, Post Process capabilities

Last Modified: August 22, 2015

Duration: 1h 5 min