Shorten Verification Time with Specman

At STMicroelectronics, engineers were presented with a C model design, with the register-transfer level (RTL) becoming available five to six weeks later. The engineers wanted to make use of this time and start their verification process. In this short video, Karl Herterich, senior IC verification engineer at the company, explains how Cadence and the Incisive Specman Elite Testbench helped the team adjust its verification environment so it could work on the C model first, then RTL for signoff. STMicroelectronics gained a shorter verification cycle in the process.

Last Modified: May 12, 2016

Duration: 2 min