The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
At STMicroelectronics, engineers were presented with a C model design, with the register-transfer level (RTL) becoming available five to six weeks later. The engineers wanted to make use of this time and start their verification process. In this short video, Karl Herterich, senior IC verification engineer at the company, explains how Cadence and the Incisive Specman Elite Testbench helped the team adjust its verification environment so it could work on the C model first, then RTL for signoff. STMicroelectronics gained a shorter verification cycle in the process.