National and Cadence Building a More Efficient Chip Design Flow

From algorithms to pre- and post-silicon validation and test, the chip design process is supported by a variety of tools and methodologies. But, as you may well know, the process isn't always very efficient. In this 4-minute video, George Zafiropoulos, vice president of Solutions Marketing at National Instruments, talks about working with Cadence to develop a more efficient chip design flow. Hear what George has to say about what happens when a prototyping platform like Cadence's Palladium® environment is connected with National's test environment for full-chip validation.

Last Modified: June 15, 2016

Duration: 4 min