Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon

Regis Santonja, Senior Mixed-Signal Verification Engineer, Freescale Semiconductor discusses the challenge of drastically reducing the size of an accelerometer without compromising performance in terms of current consumption and noise, as well as transitioning to a UVM mixed-signal environment to introduce randomization to system-level simulations. By using Cadence® Incisive® vManager™ Solution to run and analyze thousands of simulations before tapeout, his team discovered and fixed 150 bugs, resulting in bug-free final silicon!

Last Modified: June 15, 2016