Using SystemC and HLS to Evaluate Co-Processor Architectures

Andy Fox is CEO of RushC, a hardware and software consulting company. Needing to evaluate co-processor architectures for DSP applications, RushC turned to SystemC and high-level synthesis. Using Cadence's Stratus High-Level Synthesis platform, the company generated RTL from C/C++/SystemC source code and using Cadence's Encounter® tools, the company was able to evaluate the PPA using the RTL. Watch the video to learn why the company found it easier to design with SystemC than with Verilog.

Last Modified: May 10, 2016