The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
NXP's ultra-low power designs have multiple power and voltage domains, making signoff exceptionally challenging. Watch this 2.5-minute video to hear Santhosh Kumar, a senior design engineer at NXP, explain how Cadence's concurrent and distributed MMMC flows help the team overcome their challenges by consolidating all of their timing inputs into one group.