Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES

SoC designs for the mobile market obviously need to meet stringent performance and power consumption targets. In this video, Ralf Flemming, a design engineer at GLOBALFOUNDRIES, explains how the company used a Cadence® low-power digital design and signoff flow to lower leakage power to 1.5% with 2GHz maximum frequency in its ARM® Cortex®-A17 processor-based family of SoC reference designs.

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Last Modified: May 28, 2016