Physical Design Flow Challenges at 28nm on Multi-Million Gate Blocks

Nilesh Ranpura and Vineeth Mathramkote from e-Infochips discuss Physical design flow Challenges at 28nm on Multi-Milion gate Blocks. 28nm ASIC Physical design Challenges in Floorplanning, Congestion, Timing, Runtime, hold time closure. 

Last Modified: March 11, 2019