Better RTL Productivity: Learn how the Genus flow reduces unit-level iterations.

Physically Aware Context Generation: A simple Tcl command at the end of a chip- or block-level synthesis can be used to “clip” out the full timing and physical context for any subset of a design. These clips can be used to drive unit-level RTL synthesis with full consideration of chip- or block-level timing, floorplan, and placement. Using these clips can reduce unit-level iterations required to achieve timing closure by 2X.

Last Modified: May 17, 2016