The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Reducing Cost, Size of PCBs with Embedded Technologies and Cadence Layout Tools
Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications.