SAN JOSE, Calif., 23 Jan 2018
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced plans to showcase its latest Sigrity™ signal and power integrity technologies, high-speed DDR-4400 IP integration and advanced packaging solutions during this year's DesignCon in booth 711, from January 30 to February 1, 2018, in Santa Clara, Calif.
To learn more about the Cadence activities at DesignCon and register for the conference, visit https://www.cadence.com/go/designcon2018.
WHAT: Cadence experts are scheduled to discuss new developments in these technologies and how they can help solve today’s signal integrity challenges during the following speaking sessions:
- Panel—Machine Learning Advances in Electronic Design: Tuesday, January 30, 4:45 p.m. – 6:00 p.m., David White, senior director of R&D, Cadence; Christopher Cheng, distinguished technologist, Hewlett-Packard Enterprise; Paul Franzon, Cirrus Logic distinguished professor, North Carolina State University; Madhavan Swaminathan, John Pippin Chair professor, Georgia Institute of Technology
- Reduction of Mode Conversion in SerDes Links: Wednesday, January 31, 8:00 a.m. – 8:45 a.m., Mehdi Mechaik, staff application engineer, Cadence
- Temperature- and Geometry-Dependent Analysis of High-Speed PCB Traces: Wednesday, January 31, 8:00 a.m. – 8:45 a.m. and February 1, 8:30 a.m. – 9:10 a.m., An-Yu Kuo, senior group director, and Jian Liu, SI engineer, Cadence; Soumya De, SI engineer, Han Gao, SI engineer, Yaochao Yang, principal engineer, Miroslav Grubic, SI engineer, Cisco Systems
- Panel—The Impact of Machine Learning on Solution Space Analysis: Are Circuit and Channel Simulation Obsolete? Wednesday, January 31, 1:00 p.m. – 2:00 p.m., Ken Willis, product engineering architect, and Kumar Keshavan, senior software architect, Cadence; Chris Cheng, distinguished technologist, Hewlett-Packard Enterprise; Madhavan Swaminathan, John Pippin Chair professor, Georgia Institute of Technology; Dale Becker, chief engineer of electronic packaging integration, IBM; Ken Wu, staff hardware engineer and signal/power integrity manager, Google
- Panel—IBIS-AMI: New Users, New Uses: Wednesday, January 31, 3:45 p.m. – 5:00 p.m., Donald Telian, SI consultant, SiGuys; Steven Parker, principal member of technical staff, GlobalFoundries; Todd Westerhoff, VP, semiconductor relations, SiSoft; Stephen Scearce, hardware engineering manager, Cisco Systems; Ken Willis, product engineering architect, Cadence; Michael Mirmak, senior SI technical lead, Intel
- Performance Analysis for Next-Generation PCIe Interface: Thursday, February 1, 9:00 a.m. – 9:45 a.m., Mehdi Mechaik, staff application engineer, and Blake Bader, application engineering director, Cadence
- DDR-4400 IP Model Development Using AMI Builder: Thursday, February 1, 9:20 a.m. – 10:00 a.m., Chung Huang, design engineering director, and Zhen Mu, product engineering architect, Cadence
- Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard: Thursday, February 1, 10:00 a.m. – 10:45 a.m., Ken Willis, product engineering architect, Kumar Keshavan, senior software architect, and Ambrish Varma, senior principal software engineer, Cadence
- Advanced IC Packaging Trends and Their Impact on EDA Tools: Thursday, February 1, 10:15 a.m. – 10:55 a.m., John Park, product management director, Cadence
- IBIS-AMI for PCI Express Gen 4: February 1, 11:00 a.m. – 11:45 a.m., Greg Edlund, senior engineer, IBM; Mehdi Mechaik staff application engineer, Ken Willis, product engineering architect, Ambrish Varma, senior principal software engineer, and Kumar Keshavan, senior software architect, Cadence
- HSSO—Physical Structure Optimization for High-Speed Interconnects: Thursday, February 1, 11:05 a.m. – 11:45 a.m., Jack Stone, senior signal and power integrity engineer, Intel
- Brand-New Electrical and Thermal Co-Simulation Analysis: Thursday, February 1, 2:00 p.m. – 2:40 p.m., Abby Wei-Chien Chou, senior engineer, Daniel Ying-Tso Lai, senior deputy manager, and Gino Chun-Jen Chen, senior deputy manager, Foxconn
- A New Platform Power Integrity Design Approach with SPIM and UPIT: Thursday, February 1, 2:50 p.m. – 3:30 p.m., Xingjian Kinger Cai, engineering manager, Dennis Chen, platform application engineer, Jimmy Hsiao, hardware power customer engineer, Chi-te Chen, staff power integrity engineer, Yun Ling, sr. principal engineer, and Steven Yun Ji, sr. engineering manager, Intel
- Panel—Temperature and Bias-Dependent Passive Component Models: Thursday, February 1, 3:45 p.m. – 5:00 p.m., Bradley Brim, senior staff product engineer, Cadence; Istvan Novak, senior engineer, Oracle; Shoji Tsubota, engineering manager, Murata
- DDR5 Modeling Using Automated IBIS-AMI Modeling Technology: Thursday, February 1, 3:45 p.m. – 4:25 p.m., Randy Wolff, principal engineer, Micron Technology
The following demonstrations are scheduled for the show:
- Constraint-driven power integrity design and analysis, featuring easy setup with automated model and source/sink assignments
- Using patented simulation techniques to analyze equalization associated with high-speed DDR memory interfaces
- Multi-gigabit serial link design and analysis featuring compliance testing for popular interfaces such as PCI Express® (PCIe®) 4.0
- DDR-4400 IBIS-AMI model development
- Streamlining the flow between IC design and package/PCB design
WHEN: DesignCon is scheduled for January 30 – February 1, 2018
WHERE: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, Calif. Cadence is located in booth 711.
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
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