SAN JOSE, Calif., 24 Sep 2017
- Customers now have access to a set of Cadence DFM signoff solutions using Samsung advanced-node process technologies
- Qualified decks for the Cadence CMP Predictor, LPA and PVS are available in the Samsung Foundry’s standard PDKs
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its set of Design for Manufacturing (DFM) tools are now qualified on Samsung Electronics’ 28nm FD-SOI/14nm/10nm process technologies. The Cadence DFM solutions have been updated to comply with Samsung Foundry’s mandatory 28nm FD-SOI/14nm/10nm process technology requirements, enabling customers to create complex, advanced-node designs for the automotive, mobile, internet of things (IoT), high-performance compute (HPC) and consumer markets.
The Samsung Foundry’s process design kits (PDKs) for the 28nm FD-SOI/14nm/10nm process technologies are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the VirtuosoÒ platform and the InnovusÔ Implementation System, providing designers with automated fixing capabilities and overall ease of use. To learn more about the Cadence® DFM tools, please visit www.cadence.com/go/samsung28nm14nm10nm.
The Cadence DFM solutions provide the following capabilities that satisfy Samsung Foundry’s 28nm FD-SOI/14nm/10nm mandatory DFM requirements:
- LPA: The Cadence LPA provides Process Hotspot Repair (PHR) for signoff and in-design hotspot detection and fixing. The LPA fixing guidelines enable optimal fixing rates, faster runtimes, and less design perturbation.
- PVS: The Cadence PVS’s Manufacturability Analysis and Scoring (MAS) assesses the manufacturability of the design, reducing yield challenges with complex designs.
- CCP: Using a silicon-calibrated model, the Cadence CCP simulates the CMP planarity variations, detecting foundry-specific CMP hotpots and providing fixing guidelines to reduce the systematic and parametric yield loss due to CMP variations.
“We have worked closely with Cadence to deliver a qualified DFM flow so that our joint customers can meet the mandatory foundry DFM requirements, improving manufacturability of 28nm FD-SOI, 14nm and 10nm designs,” said SD Kwon, VP of Logic Process Architecture at Samsung Electronics. “The signoff flow and methodology complement our foundry capabilities, enabling customers to create the highest value by winning the time-to-market race.”
“The qualification of our set of DFM tools ensures that customer designs can meet the Samsung Foundry’s DFM standards from design implementation to signoff,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Through our collaboration with Samsung Foundry, customers using the Cadence flow can achieve optimal results with advanced-node designs, improving overall product quality.”
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
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