SAN JOSE, Calif., 18 Oct 2016
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it will showcase ARM®-optimized solutions from chips to boards to systems at ARM TechCon 2016. The event is being held October 25-27, 2016, in Santa Clara, Calif., with Cadence®, a diamond sponsor, in booth 200. To register for the conference, visit www.armtechcon.com.
WHAT: Cadence and its customers are scheduled to deliver several presentations developed for the ARM community. The speaking sessions are as follows:
- Achieving the Best PPA for a FinFET ARM Mali™-G71 GPU: Wednesday, October 26, 10:30 a.m., Room M1, Zengfu Wang, physical designer, HiSilicon
- Design Tips and Tricks to Achieve Optimal PPA for 10nm ARM Cortex®-A73 Processor: Wednesday, October 26, 11:30 a.m., Room M1, Amit Jain, deputy director, High Performance Technology, MediaTek
- Achieving Last Mile Signoff Closure in ARM Cortex-M Based Mixed-Signal Designs: Wednesday, October 26, 2:30 p.m., Room M1, Amod Srvastava, principal design engineer, NXP
- High-Performance Implementation of ARM Cortex-A53 Processor: Wednesday, October 26, 3:30 p.m., Room M1, Jay Um, senior manager of Foundry Marketing & Business Development, Samsung, and YK Lee, product engineering director of R&D Foundry, Cadence
- From IoT Idea to Silicon, Faster!: Wednesday, October 26, 4:30 p.m., Room M1, Mike Eftimakis, IoT product manager, ARM and Ian Dennison, senior group director, R&D, Cadence
- Characterization of Bitcells/Std. Cells for ARM Cores Using Massively Parallel Field Solver (3D) for FinFET Designs: Thursday, October 27, 10:30 a.m., Ballroom F, Sreenivas Aluru, staff design engineer, Process Technology Group, ARM Physical IP Division, and Hitendra Divecha, product management director, Cadence
- Helping Designers from Concept to Silicon: Thursday, October 27, 11:30 a.m., Room M3, Phil Burr, CPU product marketing manager, ARM and Kevin Yee, IP group strategic marketing director, Cadence
- Fast, Scalable and Energy-Efficient I/O Solutions for ARM-Based SoCs: Thursday, October 27, 1:30 p.m., Ballroom G, Ashwin Matta, senior product marketing manager, ARM, Andrew Swaine, senior principal engineer, ARM and Gopi Kirshnamurthy, IP architect, Cadence
- Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA® Interfaces: Thursday, October 27, 3:30 p.m., Ballroom G, Jeff Defilippi, senior product manager, ARM, Stewart Penman, solutions architect, Cadence, and Yaron Serfaty, senior software engineering manager, Cadence
Visit the Cadence "Expert Bar" in booth 200, where attendees can hold in-depth discussions on a variety of design challenge topics with Cadence subject matter experts. Throughout the two exhibit days, experts will be available on topics such as IoT design, embedded software debug and digital implementation of ARM IP. To see the full list of topics, visit the Cadence events website at www.cadence.com/go/techcon2016.
WHEN: ARM TechCon is scheduled for October 25-27, 2016.
WHERE: Santa Clara Convention Center in Santa Clara, Calif. Cadence is located in booth 200.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
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