SAN JOSE, Calif., 15 Feb 2016
The Innovus Implementation System offers customers key technologies for using the Samsung 10nm process including the GigaPlace™ solver-based placement technology, a slack-driven, pin access-aware placer that improves electrical and physical design convergence at advanced nodes. The tool also offers integration with the Cadence Quantus™ QRC Extraction Solution, the Tempus™ Timing Signoff Solution, the Voltus™ Power Integrity Solution and the Physical Verification System, all of which enable design convergence for faster design closure. The Innovus Implementation System incorporates a massively parallel architecture that increases capacity and drives better turnaround time without compromising PPA. For more information on the Innovus Implementation System, please visit www.cadence.com/innovus.
"We have collaborated with Samsung to enable customers to deploy production flows on 10nm FinFET designs in order to achieve the best PPA and overcome design complexity to meet aggressive time-to-market demands," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "We are actively working with customers on new designs on the Samsung 10nm process using the Innovus Implementation System, and we are seeing early successes that can enable these designers to stay in front of the competition."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
For more information, please contact: