SAN JOSE, Calif., 31 Jan 2016
The simple, single-pass Cadence flow provides designers with guidelines to optimize their PowerVR GPU cores via documentation and scripts that are easy to deploy and support. The flow includes the following Cadence digital and signoff tools:
- Innovus™ Implementation System: A next-generation physical implementation tool that incorporates a massively parallel architecture, enabling SoC developers to deliver high-quality designs with highly competitive power, performance and area (PPA)
- Genus™ Synthesis Solution: An RTL synthesis and physical synthesis engine that mitigates productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times and up to 20 percent datapath area reduction, while scaling linearly beyond 10M instances
- Tempus™ Timing Signoff Solution: A complete timing analysis tool that reduces signoff timing closure through massively parallel processing and physically aware timing optimization
- Conformal® Equivalence Checker: The industry's most widely supported independent formal verification solution enabling the verification and debug of multi-million-gate designs without using test vectors
- Quantus™ QRC Extraction Solution: A next-generation parasitic extraction tool that is production proven and provides faster runtimes for single- and multi-corner extraction and best-in-class accuracy versus the foundry golden
"As a leading graphics technology, PowerVR GPUs are found inside some of the world's most popular products," said Tony King-Smith, EVP marketing at Imagination. "Our customers care deeply about the speed and footprint of our highly scalable GPUs in their production chips. We collaborated with Cadence to help them create this reference flow based on Cadence digital and signoff tools that help our licensees bring to production smaller, faster chips in less time."
"We see a significant opportunity for our joint customers to achieve improved PPA using the new Cadence digital and signoff reference flow on Imagination's PowerVR GPUs," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "By focusing on the complex needs of today's designers, we successfully created an optimal flow for PowerVR that surpasses the results of previous flows and enables our many customers using PowerVR GPUs to bring reliable, innovative designs to market more rapidly."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
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