SAN JOSE, Calif., 16 Nov 2015
- New Palladium Z1 enterprise emulation platform delivers up to 5x greater emulation throughput, with an average 2.5x greater workload efficiency than its closest competitor
- Datacenter-class emulation scalability from IP blocks to full Systems-on-Chip with capacity of up to 9.2 billion gates
- Delivers best in class total cost of ownership with 92 percent smaller footprint, 8X higher gate density and up to 44 percent better power density than the Palladium XP II platform
- With the ability to execute up to 2304 parallel jobs with 4 million gate granularity, and unparalleled reliability, Palladium Z1 platform is already being utilized across global design teams to verify increasingly complex designs
"The design and verification of our very complex devices requires us to employ sophisticated tools such as hardware emulation for fast and reliable system development," said Narenda Konda, director of engineering at NVIDIA. "Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule."
For more on NVIDIA's experience, please see the video at www.cadence.com/news/PalladiumZ1/Nvidia
A true datacenter resource enabling maximum utilization, Palladium Z1 enterprise emulation platform features a rack-based blade architecture to provide enterprise-class reliability, a 92 percent smaller footprint and 8X better gate density than the Palladium XP II platform. Optimizing the utilization of the emulation resource, Palladium Z1 platform offers a unique virtual target relocation capability, and payload allocation into available resources at run time, avoiding re-compiles. With its unique massively parallel processor-based architecture, Palladium Z1 platform offers 4X better user granularity than its nearest competitor.
"For our advanced SoC designs we are facing thousands of verification payloads of varying sizes from dozens of different projects," said Daniel Diao, deputy general manager of the Turing Processor Business Unit at Huawei. "The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four million gate verification payloads to multi-billion gate designs, allowing us to ensure system functionality in short project schedules."
Additional key features and benefits of the Palladium Z1 platform include:
- Less than one-third the power consumption per emulation cycle of the Palladium XP II platform. This is enabled by an up to 44 percent reduction in power density, an average of 2.5X better system utilization and number of parallel users, 5X better job queue turnaround time, up to 140 million gate per hour compile times on a single workstation, and superior debug depth and upload speeds
- Full virtualization of the external interfaces using a unique virtual target relocation capability. This enables remote access of fully accurate real world devices as well as virtualized peripherals like Virtual JTAG. Pre-integrated Emulation Development Kits are available for USB and PCI-Express® interfaces, providing modeling accuracy, high performance and remote access. Combined with virtualization of the databases using Virtual Verification Machine capabilities, it allows for efficient offline access of emulation runs by multiple users
- The industry's highest versatility with over a dozen use models, including In-Circuit Emulation running software loads, Simulation Acceleration that allows hot swapping between simulation and emulation, Dynamic Power Analysis using Cadence Joules™ RTL power estimation, IEEE 1801 and Si2 CPF based Power Verification, Gate-level acceleration and emulation, and OS bring-up for ARM-based SoCs running at 50X the performance of pure standard emulation
- Seamless integration within the Cadence System Development Suite. This includes Incisive® verification platform for simulation acceleration, Incisive vManager™ for verification planning and unified metrics tracking, Indago™ Debug Analyzer and Embedded Software Apps for advanced hardware/software debug, Accelerated and Assertion-Based Verification IP, Protium™ FPGA-based prototyping platform with common compiler, and Perspec™ System Verifier for multi-engine system use-case testing
For more information on the Palladium Z1 enterprise emulation platform, please visit www.cadence.com/news/PalladiumZ1.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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