SAN JOSE, Calif., 10 Mar 2015
- Provides typical 10 to 20 percent production-proven advantage in power, performance and area
- First massively parallel implementation solution in the industry, enabling unprecedented speed and capacity
- Supports advanced 16/14/10nm FinFET and established process nodes
- Next-generation platform eases usability and boosts engineering productivity
For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.
The Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency. The key Innovus capabilities to achieve this include:
- New GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization
- Advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance
- Unique concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power
- Next-generation slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation
- Full-flow multi-objective technology enables concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA
In addition to providing best-in-class PPA and optimized turnaround time, the Innovus Implementation System offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus™ Timing Signoff solution and Quantus™ QRC Extraction solution. Together these solutions enable fast, accurate, 10nm-ready signoff closure that facilitates ease of adoption and an end-to-end customizable flow. Customers can also benefit from robust visualization and reporting that enables enhanced debugging, root-cause analysis and metrics-driven design flow management.
"At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets," . "We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target. Based on our results, we are confident that the new physical implementation solution can help our mutual customers deliver complex, advanced-node SoCs on time."
"Customers have already started to employ the Innovus Implementation System to help achieve higher performance, lower power and minimized area to deliver designs to the market before the competition can," said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "The early customers who have deployed the solution on production designs are reporting significantly better PPA and a substantial turnaround time reduction versus competing solutions."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
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