SAN JOSE, Calif., 01 Jun 2014
"As the premier supplier of high-performance silicon solutions for energy-efficient electronics, ON Semiconductor believes it is important that we continue to enhance our design flows to keep pace with our customers' demands for lower power consumption and faster time to market," said Martin Kejhar, senior technical staff engineer and scientist at ON Semiconductor. "Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block."
Virtuoso Layout Suite EAD is a unique, patented in-design electrical verification capability that enables design teams to monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the design specifications. It allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance. For more information on Virtuoso Layout Suite EAD, visit: www.cadence.com/news/ead.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and services is available here.
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