SAN JOSE, Calif., 10 Dec 2014
- Reduces complex use-case scenario development effort for SoC verification from weeks to days
- Automates traditionally manual, and often complex, system-level coverage-driven test development
- Improves SoC quality by accelerating the development of complex software-driven tests and integrated debug to reproduce, find and fix complex SoC-level bugs
Perspec System Verifier is currently available. For more information, visit www.cadence.com/news/perspec.
Perspec System Verifier delivers increased productivity and SoC quality through several key features, including:
- A Unified Modeling Language (UML) based view of system-level actions and resources that, combined with powerful solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions
- Solver technology, which automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios to verify SoC-level features for functionality, performance and power
- Tests that run on all pre-silicon verification platforms including simulation, acceleration and emulation, and virtual and FPGA prototyping, which can be further used to validate actual silicon
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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