SAN JOSE, Calif., 18 Nov 2013
"As the global leader in manycore processors, it is critical that Tilera selects the best design signoff technologies to achieve optimum performance-per-watt in our products while meeting aggressive time-to-market requirements," said John F. Brown III, vice president of IC Engineering at Tilera. "The Voltus product's advanced parallel computation significantly reduced the power signoff runtime on our most recent TILE-Gx processor. This superior performance allows our engineers to cut the power signoff iteration procedure from days to hours and achieve the best in quality in our designs."
The enabling technologies behind the Voltus IC Power Integrity Solution include a new massively distributed parallel power integrity engine and hierarchical analysis technology that can run designs of up to 1 billion instances and with up to 10X performance gains over competing products. The Voltus solution can be used as a standalone power signoff tool, but it provides even greater value to its users through its integration with several key Cadence tools - the Tempus™, Encounter®, Palladium®, Allegro®, Sigrity®, and Virtuoso® platforms. This combined design implementation and signoff eco-system provides the industry's most efficient and fastest design closure flow.
Learn more about Voltus IC Power Integrity Solution at www.cadence.com/news/Voltus.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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