Today, most design verification happens with SystemVerilog-based testbenches or UVM—which leads to the misunderstanding that the language is used solely for verification. The fact is, that SystemVerilog has excellent features that can be used for writing synthesizable RTL code.
This webinar—complete with examples—will highlight several SystemVerilog features that let you write synthesizable RTL code.
- New design constructs and relaxation of datatype rules
- Specialized procedural blocks
- Enumerated types and case constructs
- Q & A
To register for the “Why Consider SystemVerilog for Synthesizable RTL” webinar, just sign in below with your email and Cadence password, then select “Request“ to register for the session. Once registered, you’ll receive a confirmation email containing all log-in details.
- Registration closes Monday, May 27
- Please ensure that you have received the log-in link / details by this date
- Seating is limited for this webinar—if you register, please plan on attending
- Webinar attendees will receive a SystemVerilog Quick Reference Guide
For questions and inquiries, or issues with registration, reach out to us.
To view our complete training offerings, visit the Education Services website.