Join Cadence in booth #30 at the International Wafer-Level Packaging Conference (IWLPC). This conference is the premier event that brings together wafer-level packaging, 3D, advanced manufacturing, test technologies, and education in an environment of cooperation and technical exchange.
In the booth, we will showcase the Cadence® SiP Layout Advanced WLP Option technology which offers:
- Integrated system design solution for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology, including implementation, signoff, and electro-thermal analysis tools that enable concurrent multi-chip optimization
- Direct integration with PDK-driven PVS DRC/verification providing graphical designer feedback minimizing path to tapeout readiness
- Advanced WLP-specific metal creation and management removing/reducing eco spins
- Shortened path to tapeout readiness with high-performance GDSII processing
- Production- and foundry-proven flow with multiple tapeouts