Join us to celebrate the 50th anniversary of GOMACTech and 50 years of advanced technology. Visit Cadence at booth 608 and see our aerospace and defense technologies that provide proven, reliable, and seamlessly integrated capabilities for designing and analyzing electronics systems. Our customers, including the top 10 aerospace and defense manufacturers, use our software, hardware, IP, and services to design and verify advanced semiconductors (with reference flows beyond 10nm), IC packaging, PCBs, and systems. We offer a complete rules-driven design and analysis environment needed to meet rigorous industry requirements, including an ITAR-compatible design infrastructure that enables users from multiple organizations to collaborate on complex designs in a secure environment. Contact Us to schedule a meeting during the conference, or attend one of these sessions to hear more about Cadence® solutions:
Wednesday, March 14, 3:30pm – 4:50pm
Session 23: Secure Design
23.5 - Enabling Foundational Hardware Security Through the Use of Emulation
Presented by Jason Oberg of Tortuga Logic, Inc. and Steve Carlson of Cadence Establishing foundational secure hardware architecture and architectural implementation is a necessary first step in creating secure electronic systems. Nonetheless, establishing the security of a design has remained a cumbersome, open-ended process. One of the issues that makes hardware security verification difficult is the absence of integration with later-stage verification technologies/engines. The enormous device counts and associated intractable state spaces mean that early-stage verification engines such as formal and simulation alone cannot perform all of the necessary analysis. Application of emulation technology enables the security verification process to reach into the “deep cycles” portions of the state space that are controlled by copious amounts of both hardware and software. This paper examines the issues in applying emulation technology, and assesses the best practices for verification coverage on those elements of the security verification plan that cannot practically be addressed via formal or simulation engines.
Thursday, March 15, 3:30pm – 4:50pm
Session 38: Digital Design Techniques for Advanced Chips
38.4 - Towards “Systems of Systems” Verification for Systems on Chips in Aerospace Applications
Presented by Frank Schirrmeister, Cadence This paper will analyze the challenges for a verification flow for electronic devices and systems. Using practical customer examples, we will outline the benefits of integrating multiple discrete components into SoCs and introduce a verification methodology that takes into account aspects of functional safety, system complexity, and design-to-test aspects in the aerospace application domain.