CDNLive Taiwan 2018
August 14, 2018
Ambassador Hotel, Hsinchu, Taiwan
(新竹國賓大飯店)
CDNLive Taiwan 2018 brought together Cadence® technology users, developers, and industry experts for a day of networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
Cadence Taiwan 2018 welcomed a record-breaking number of attendees from customers, exhibitors, and partners who gathered to connect, share, and inspire!
Highlights of CDNLive Taiwan 2018:
Technical Sessions
This year’s conference featured over 40 presentations from six different technical tracks, including a wide variety of user-authored presentations addressing all aspects of design and IP creation, integration, and verification. Designers discovered how others are using Cadence technologies and techniques to design silicon, SoCs, and systems efficiently and profitably.
Executive Keynote Speakers
Tom Beckley, Sr. VP and GM, Custom IC & PCB Group (CPG) shared “Enabling the Fourth Industrial Revolution (4IR) Cadence System Design Enablement.” Steven Liu, Sr. VP of UMC shared about “IC2.0: Next-Generation IC for an Intelligently Connected World”. Dr. CP Hung, RD VP of ASE Group, talked about “New SiP Technology and Design Challenges” and the collaboration with Cadence on an SiP-id EDA solution. David Pellerin from Amazon Web Services shared “Innovation in Cloud-Based EDA for IoT, AI, and Semiconductor Design.”
Networking Opportunities
The networking luncheon offered an informal atmosphere to engage in stimulating technology discussions with Cadence technologists.
Designer Expo
More than 12 exhibitors participated in the Designer Expo, highlighting the collaborative ecosystem available to support you.
Presentation Awards
Congratulations to our CDNLive Taiwan 2018 Best and Outstanding Presentation Award Winners!
Best Presentation Award
Track: (PCB) IC Packaging and PCB Design
A New Concept in Power Distribution Network Design of Multi-Core Processor
Nansen Chen (陳南璋), MediaTek
Outstanding Presentation Awards
Track: IC Packaging and PCB Design
Design and Optimization for the Next Generation High Speed Connector
Joe Chen (陳建勳), Foxconn
Track: IC Packaging and PCB Design
IBIS-AMI Modelling with Dummy IBIS in PCIe 4.0 PHY Design
Huaide Wang (王懷德), M31
Track: Analog and Mixed Signal
Improving Analog Circuit Design Robustness with Cadence Based Analog Device Matching Checks
I-Lun Tseng, Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, and Jonathan Ong, GLOBALFOUNDRIES
Track: System Design / Verification
Use JasperGold SEC to Verify FPU
Chia-I Chen (陳嘉怡), Realtek
Track: Digital Design and Full Flow
Incremental IR Drop Analysis on Large Scale Design for Fast ECO Iterations
Chee-Kong Ung (洪志光), MediaTek
Winnie Pao (包洵瑋), MediaTek
Contact Us
Questions?
Email TW_CDNLive@cadence.com
