CDNLive Silicon Valley 2017
April 11-12, 2017
Santa Clara Convention Center – Santa Clara, CA
CDNLive Silicon Valley brought together a record number of Cadence® technology users, developers, and industry experts for two days of networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
Highlights of CDNLive Silicon Valley 2017:
Technical Sessions
This year’s conference featured more than 100 presentations from 11 different technical tracks, including a wide variety of user-authored presentations addressing all aspects of design and IP creation, integration, and verification. Designers discovered how others are using Cadence technologies and techniques to design silicon, SoCs, and systems efficiently and profitably.
Keynote Speakers
Lip-Bu Tan (Cadence President and Chief Executive Officer), Kushagra Vaid (Microsoft General Manager and Distinguished Engineer – Azure Hardware Infrastructure Cloud + Enterprise Division), and Anirudh Devgan (Cadence Executive Vice President and General Manager, Digital & Signoff Group and System & Verification Group) each presented engaging, insightful talks on industry trends, challenges, and opportunities in electronic design.
Designer Expo
More than 25 exhibitors participated in the Designer Expo, and highlighted the collaborative ecosystem available to support you. Cadence and our partners enjoyed lunch and an evening reception mingling with customers and exploring joint solutions.
View Sponsors & Exhibits
Networking Opportunities
The R&D luncheon offered an informal atmosphere to engage in stimulating technology discussions with Cadence technologists and industry peers.
Best Presentation Awards
Congratulations to our CDNLive Silicon Valley 2017 Best Presentation Award Winners!
Track: Academic
ACA207: Agile Hardware Design with a Generator-Based Methodology
Elad Alon, UC Berkeley
Track: Custom / Advanced Node
CUS201: Control File-Driven Constraints for Route Ready Placement
Julia Perez, NXP Semiconductors
Track: PCB Design
DES207: Designing High-Speed Signals with Cadence Allegro Design Suite
Bryan LaPointe, Freedom CAD Services
Track: Front-End Design
FED104: Rapid Turns with Palladium and Joules
Theodore Wilson, Microsemi
Track: Digital Implementation / Advanced Node
FFA203: Dial in Innovus Timing Correlation with Signoff Tools and Why Not Wait Until You "Aren't As Busy"
Jack Benzel, Broadcom
Track: IP / Block Verification
IPB105: Power Management AMS Verification for Battery Dropout in Automotive Applications
Abhishek Kumar, NXP Semiconductors
Track: Mixed-Signal Design
MIX103: UVM Mixed-Signal Verification without Prior UVM Experience
Greg Happel & Michael Hageman, Rockwell Collins
Track: PCB Simulation
PCB105: WEBENCH Allegro Connector
Pradeep Chawda, Texas Instruments
Track: Signoff
SIG202: Using Pegasus for Advanced Node Physical Verification
Scott Barrick, Microsemi
Track: Tensilica Processors and Design IP
TIP104: The Use of Forward Error Correction in the Cadence DisplayPort 1.4 IP Core
Tim Corcoran & Avrum Warshawsky, Hardent
Track: SoC / System Verification
VER104: Validating Complex Multi-GPU Configurations with Virtual Emulation
Satyadev Muchukota, NVIDIA
Contact Us
Questions?
Email cdnlive@cadence.com
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