CDNLive Boston 2016
August 31, 2016
Boston Marriott Burlington – Burlington, MA
CDNLive Boston brought together a record number of Cadence® technology users, developers, and industry experts for two days of networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
Highlights of CDNLive Boston 2016:
Technical Sessions
This year’s conference featured more than 40 presentations from 8 different technical tracks, including a wide variety of user-authored papers addressing all aspects of design and IP creation, integration, and verification. Designers discovered how others are using Cadence technologies and techniques to design silicon, SoCs, and systems efficiently and profitably.
View Proceedings
Keynote Speakers
Daryn Lau (Corporate VP and GM, Research & Development at Cadence), Paul Cunningham (VP Research & Development for Digital and Signoff Group at Cadence), and Dr. William Chappell (Director, Defense Advances Research Projects Agency (DARPA)) each presented engaging, insightful talks on industry trends, challenges, and opportunities in electronic design.
Designer Expo
13 exhibitors participated in the Designer Expo, and highlighted the collaborative ecosystem available to support you. Cadence and our partners enjoyed lunch and an evening reception mingling with customers and exploring joint solutions.
Networking Opportunities
Networking dinners, a Happy Hour in the Designer Expo, and an entertaining Evening Event offered an informal atmosphere to engage in stimulating technology discussions with Cadence technologists and industry peers.
Best Paper Awards
Congratulations to our CDNLive Boston 2016 Best Paper Award Winners!
Custom IC/Analog Design
CUS106: GLOBALFOUNDRIES 14LPP-XL ESD Solution and Implementation Flow for FinFET Designs
Jignesh Patel, GLOBALFOUNDRIES
SI, PI, and Simulation
SIP102: Mid-Frequency Noise Coupling Between DC-DC Converters and High-Speed Signals
Laura Kocubinski, Oracle
System/Verification - SoC and Hardware/Software
SOC105: Real-World Use of Metric-Driven Verification on Mixed-Signal Designs
Dan Romaine, Teradyne
System/Verification - IP and Subsystem
SUB106: Using Formal Verification for Silicon Debug and More
David Brownell, Analog Devices
PCB and IC Packaging
PCB103: Designing High-Speed Signals with Cadence Allegro® Design Suite
Brian Lapointe, FreedomCAD
In-Design and Signoff Verification
SIG103: MS Power Analysis with Voltus™/Voltus-Fi Technologies
MD Salam, Allegro Microsystems
Digital Flow
DIG106: System-Level Design and High-Level Synthesis for Embedded Scalable Platforms
Luca Carloni, Columbia University
Special Topics
SPT101: RFIC Design Using Cadence's Hosted Design Services
Jack Holloway, Naval Research Laboratory
CDNLive Mobile App Grand Prize Winner
At the close of the event, the top 20 attendees on the CDNLive Mobile App Leaderboard had their names entered into our grand prize drawings. Congratulations to the iMac winner A Gutmann from Analog Devices!
Contact Us
Questions?
Email cdnlive@cadence.com
