Reports from the Conference
Snapshot of Wednesday’s Sessions at CDNLive Silicon Valley
March 13, 2013
On Wednesday at CDNLive Silicon Valley, attendees continued to connect and share techniques and tips during a variety of technical sessions.
Gagandeep Singh, a Product Engineer on the Cadence® Incisive® R&D team, presented, “Addressing Renewed Gate Level Simulation Needs at 20nm-40nm and Below.” Timing has become more complex, Singh noted, as designs increase in size and complexity. Why gate level simulation (GLS)? GLS can overcome limitations of static timing analysis (STA), verify system initialization and the accuracy of the reset sequence, provide design for test (DFT) verification, and supply a switching factor to estimate power, among other benefits.
Singh discussed some techniques to enhance performance of GLS while running the Cadence Incisive Enterprise Simulator, including applying more zero-delay simulation when the design is in the process of timing closure and controlling gate delays.
In “Designing with 14nm FinFET Technology, “ Wei Lii Tan, a Sr. Product Marketing Manager, talked to a packed room about design challenges at 14nm that can be resolved with FinFET technology. He also emphasized the value of working closely with foundry and other industry partners, as collaboration is a key to solving these design challenges.
Cadence is currently teaming with IBM and ARM® on a variety of 14nm experiments to assess the yield impact of bidirectional routing. The collaboration has already resulted in the first 14nm test-chip based on an ARM Cortex™-M0 processor and using IBM’s FinFET process technology.
Sharing is one of the themes of this year’s CDNLive, and this was evident in Singh’s GLS session, as attendees discussed practical applications of GLS techniques, working with layout teams to extract the correct files, and more. Presenters encouraged attendees to regularly share their input and work with Cadence to solve the challenges of designing at shrinking process nodes.
CDNLive Silicon Valley 2013 Keynotes
March 12, 2013
Connect. Share. Inspire. That’s the theme of this year’s CDNLive Silicon Valley user conference hosted by Cadence. Looking at the packed ballroom for the event’s keynotes on Tuesday morning, there certainly was plenty of connecting, sharing and inspiration.
In his keynote address, “Exciting Opportunities for Great New Products,” Cadence CEO and President Lip-Bu Tan told the crowd, “This is a very exciting time. We have a lot of new gadgets, new products that enable a quality of life….from 3D TV, to Google Glass to wearable devices that monitor your health. The Internet of Things is really kicking off. Hopefully, we are true partners who can help each of [these technology companies] design great products.”
Mobile, social media, cloud, the Internet of Things, and big data are among the trends driving development. Semiconductors are at the heart of electronic devices, from home entertainment systems to wireless appliances to gaming equipment and much more. Yet, designers are facing greater challenges as the industry moves to smaller processes, chip design becomes increasingly complex, development costs continue to rise, and time-to-market pressures continue. “We are intelligent engineers, we always find ways to solve problems,” Tan said. “Clearly, a lot of innovation is needed. Let’s solve the problems so we can extend Moore’s Law and drive new designs that we all enjoy. Our end result is to make sure we delight our customers’ customers.”
Next on tap was Young Sohn, President and Chief Strategy Officer of Samsung Electronics, who carried the thread in, “Today and the Future.” Technology brands, he noted, are becoming consumer brands. “We are an essential part of how we live, how we share, and how we connect,” he said.
Sohn outlined the vision for Samsung Electronics: seamless sharing of media content anywhere, anytime, and with any device. “What is possible is really up to our imagination, and much of the technology behind it is semiconductor technology. We believe this mobile vision is much greater than being able to send a text, emailing, and web access. The post-PC era has more to do with what’s coming, a new wave of opportunities. The partnerships between EDA companies and Samsung need to be closer.”
Closing out the keynote session was Martin Lund, Senior Vice President of R&D for the SoC Realization Group at Cadence. In his talk, “SoC Challenges and Application-Optimized IP,” Lund noted that, as design challenges continue, the old ways of doing things may no longer work. Standard building blocks may not fit an SoC’s requirements; the approach of IP reuse, as a result, may be challenged.
In this climate, there’s a growing need to build IP to meet the requirements of the SoC. Next-generation IP, Lund explained, is quality focused, integration optimized, requirements driven and designed to deliver what the SoC designer needs, no more and no less. He closed his keynote by highlighting Cadence’s proven track record in Design IP and its market-leading position in verification IP. Lund added, “We are committed to building great relationships with you and your colleagues.”
System to Silicon Verification – How It All Fits Together
March 12, 2013
Frank Schirrmeister, a Cadence® senior director in the System and Software Realization Group, kicked off the system technical track at CDNLive Silicon Valley on Tuesday with “System to Silicon Verification – How It All Fits Together.”
Schirrmeister outlined how systems as well as vendor roles have evolved over the years. Using the example of a cell phone, circa 2004, Schirrmeister pointed out the inner workings of a system: I/Os, modem processing, multimedia processing, memory, power management, lots of passive components, packaging, and lots of software. “From a chip perspective, that looks like a system, but a system is really a matter of perspective,” he noted. “That system, a phone in this case, is only a small component in the overall network of things. A system always becomes a component in a different context.”
Looking into the future, a chip is likely to involve more complex designs, more design starts at under 90nm, and overall fewer design starts. Driving these factors: requirements around feature sets and user experience, low power consumption, and time to market.
How does this impact product creation? “Everyone in the supply stack will need to supply more,” said Schirrmeister. “There is no one engine that allows us to do it all.”
He then discussed the Cadence® System Development Suite, introduced in 2011 to provide a platform continuum with a common environment. “The design seamlessly goes through different engines and different engines can be connected. Are we there yet? Not completely, but we’re getting better.”
The 2012 version of the Cadence System Development Suite provided an integrated approach with an open, connected, and scalable suite including the Cadence Virtual System Platform, the Cadence Rapid Prototyping Platform, the Cadence Incisive® functional verification platform, and the Cadence Palladium® XP Verification Computing Platform. The vision for the suite calls for the solution to progress from a set of initial, connected engines to a platform that provides seamless interaction between all of the engines.
“It’s very exciting for me to see this flow become a reality and to see the interaction between the different engines becoming reality,” Schirrmeister concluded.
Soundbytes from Tuesday’s Technical Tracks
March 12, 2013
Tuesday’s technical tracks at CDNLive Silicon Valley covered a variety of topics, from analog interface signal coverage checking to system-level debug productivity, design rule verification using RAVEL, scalable and programmable memory BIST solution, and much more.
In, “Is Super-Speed Interconnect Revolutionizing the Mobile Design?,” Huz Dalal, Sr. Product Marketing Manager for the Cadence® Verification IP (VIP) team, and
Rishubh Garb, USB Verification IP R&D Lead at Cadence, provided an overview of the USB Super-Speed Interchip (SSIC), the scalable, chip-to-chip interconnect solution for Super-Speed USB. “I haven’t heard so much excitement for USB than in this year,” Dalal noted.
Garb talked about the challenges involved in verifying USB 3.0 and the unique verification requirements to consider in each verification step. He outlined the Cadence Verification IP for USB 3.0, which delivers benefits including dynamic SOMA configuration and register interface to control functionality, and PureSuite™ USB 3.0 compliance solution, which is built in SystemVerilog.
In “Advances in Client-Server Technology for More Verification Automation,” John Brennan, marketing director at Cadence, talked about high-performance computing and its impact on electronic design automation (EDA).
“Verification is a team sport, everyone needs to participate,” Brennan said. Because design teams can be dispersed in locations across the globe, high-performance computing is an important tool that allows dispersed teams to function as one.
In particular, functional verification planning and management provides a great opportunity for high-performance computing. Advantages include improved collaboration, coordination, and controllability. “You can see exactly where to apply more testing,” he noted.
To plan for a high-performance client/server implementation, Brennan suggested several guidelines: running Linux RedHat V5, investing in high-performance storage, maintaining a strong network, and implementing the right hardware based on application needs.
Patrick Gallagher, a Cadence architect, presented, “Scalable, Programmable Memory BIST Solution for Your Needs Today and Tomorrow.” As the total die area devoted to memory continues to increase, a number of challenges has emerged, including impacts to design schedules and yield, Gallagher noted.
Gallagher discussed the three key steps for memory BIST (definition, insertion of instructions, and verification), and he contrasted memory views vs. configuration files. He discussed three testing approaches, compared pre-defined and user-defined algorithms, and provided an overview of testplan specifications.
Challenges in this realm can be met by performing an analysis of the design to allow target memory testing at the proper level. Proper targeting then sets the stage for minimal design impact. There should be flexibility in developing algorithms, and in allowing for a means to test memory with built-in algorithms.