Taking on a complex SoC or multichip system is a daunting task, yet design teams are expected to achieve a predictable process. Multiple design groups contribute circuit specifications upfront and often use disparate methodologies to design blocks independently from each other—yet these design pieces must integrate seamlessly from both a physical design and a simulation/verification perspective.
Two primary design challenges are discussed here:
Predictability of performance and schedule
Predictability is based on two primary concerns:
1. meeting schedule from the beginning of the design process, which necessitates a fast path to tape-out, and
2. meeting performance requirements to achieve first-pass success, which requires silicon accuracy.
Meeting schedule requires a design process that supports thorough and complete simulation for analog and mixed-signal circuits in both schematic and behavioral model form. The design process consists of numerous tasks: setting specifications, design entry, model creation, block simulation, design optimization, and system verification. In addition, many of today's chips contain multiple blocks from multiple design domains.
Using a top-down design process brings the project to tape-out faster by supporting a mixed-level approach that replaces behavioral models with detailed design at only the areas needed for a given test. This also allows for leveraging top-level system IP, using that information for block specification and design, and subsequently re-verifying the top-level blocks as they are modified for the current application.
Silicon accuracy is driven from the bottom-up design process through detailed transistor-level analysis using sophisticated models, and then verifying the system specification through layout extraction of the parasitics. With this information, calibrated models of detailed design blocks can be created to provide higher levels of abstraction for top-down system simulations. Design specification
When beginning a design task, the designer first needs to determine the specifications that need to be met. For an analog/mixed-signal block, some of those specifications may be bandwidth, delay, gain, thresholds, output current, power supply voltage and current levels. Setting clear specifications for a block will speed up the overall design process by clarifying the interface with the rest of the system, thus minimizing redesigns at the last minute. Design entry
Top-level design is usually hierarchical, which each level in the hierarchy connecting various design blocks together and communicating with higher and lower levels. For analog/mixed-signal designs, the design entry is usually done in a schematic, where blocks are represented by symbols containing another level of hierarchy, a schematic of components, or a language-based model of behavior or structure. Model creation
In a mixed-level hierarchy, behavioral blocks are used to represent a schematic's performance either before or after the detailed design work is done. Models can be crafted to represent desired behavior using a language, such as Verilog-A, or they can be constructed after the fact by a model-fitting program such as Virtuoso Characterization and Modeling Environment. Block simulation
An analog/mixed-signal block is a self-contained design entity that performs a specified function, and can be tested alone using a test-bench of drivers and loads. Before incorporating a block (whether schematic-based, or language-based) into a system, it is important to verify that the block functions as expected and meets the pre-determined specifications for that block. This is done by using a simulator, which exercises the block in ways chosen by the designer, and produces graphical or text-based output that becomes part of the design collateral for communication and review. Design optimization
Once the basic design of the block is completed at the transistor level, the designer will want to exercise it over all the limits of expected operation, such as voltage, temperature, and process extremes. This can be done by repetitive simulations, or by using scripts to control the multiple simulation runs and issuing reports. Another methodology is to use an optimization program to analyze the design through simulation, and recommend component value changes to increase yields to specification. System verification
A system is a collection of design blocks that are organized to perform a specified function. If one block is defective, or performing out of its specified operating range, then the system function may not be accomplished. This requires a verification program that can run simulations for very large analog and digital designs, both at the schematic level, extracted netlist level, and using behavioral language descriptions. For extremely large designs, including large memory arrays or repetitive blocks, a FastSPICE simulator is often necessary. For verifying systems that include extracted parasitics from layouts, advanced RC reduction techniques are required to obtain results in a reasonable time-frame.
Leveraging legacy ip from previous designs
Leveraging legacy IP from previous generation designs, or producing a derivative from a large SoC, further complicates the process, while at the same time accelerating the drive to tape-out. The complication comes from differing market requirements and specifications, second sourcing for fab capacity, or migrating to a new process technology to enhance performance or reduce cost. All of these IP migrations and modifications require additional design customization over pure digital designs. Yet, architectures and test setups are often highly leverageable (i.e., simulation testbenches, design and layout topologies, and design process) and are high-value starting points for the migration or modification effort. To learn more about modern mixed-signal design challenges, consult the Advanced Custom Design Methodology white paper.
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