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In this course, you learn about the features of the Cadence® Encounter® RTL Compiler with global synthesis technology. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT constraints, and interface with other tools. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files. You also learn to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power.
After completing this course, you will be able to:
- Apply the recommended global synthesis flow using Encounter RTL Compiler
- Navigate the design database and manipulate design objects
- Constrain designs for global synthesis and run static timing analysis
- Optimize RTL designs for timing and area using several strategies
- Diagnose and analyze synthesis results
- Use the extended datapath features of the compiler
- Analyze and synthesize the design for low-power structures
- Optimize designs using the physical synthesis flow
- Constrain the design for testability (DFT)
- Identify the interface to Encounter Conformal® equivalence checker and other tools
Software Used in This Course
- Encounter RTL Compiler with Physical
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
- About This Course
- Overview of Encounter RTL Compiler
- RTL Compiler Synthesis Flow Fundamentals
- Datapath Synthesis
- Optimization Strategies
- ASIC Designers
- Digital IC Designers
- Logic Designers
You must have experience with or knowledge of the following:
- Any HDL such as Verilog (recommended) or VHDL
- Synthesis and ASIC design flow basics
- Static Timing Analysis
Or you must have completed the following courses:
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