In this course, you learn to verify low-power designs using Conformal® Low-Power Verification. In the labs, you debug practical examples of common power format (CPF) or IEEE 1801 violations, functional and structural violations, and nonequivalences.
After completing this course, you will be able to:
- Identify features of Conformal Low-Power software
- Identify the flows for low-power verification
- Identify power intent support in Conformal Low-Power software
- Apply low-power checks on gate netlists with corresponding power intent
- Apply low-power checks on physical netlists with corresponding power intent
- Run low-power equivalency checks in different stages along with the supplied power intent
Software Used in This Course
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
- Preparation and Setup
- Power Intent Support (Si2 CPF and IEEE 1801)
- Synthesis Verification
- Physical Verification
- Using Conformal Low-Power Successfully
- Design Engineers
- Digital IC Designers
- FPGA Designers
- Hardware Engineers
- Logic Designers
- Verification Engineers
You must have experience with or have knowledge of the following:
- Have a basic understanding of Verilog language and constructs
- Have a basic understanding of one of the three CPF, UPF, or IEEE 1801 power intent formats
- Completed Logic Equivalence Checking with Conformal course or
- Have equivalent experience with the Conformal Equivalence Checker tool
Or you must have completed the following courses:
- Logic Equivalence Checking with Conformal EC
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Click here to view course learning maps, and here for complete course catalogs.