This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro® Package Designer, or the Allegro® Design Entry HDL Front-to-Back Flow course.
In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver and receiver pairs.
This course requires SPB17.2-2016 software or later.
After completing this course, you will be able to:
Software Used in This Course
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
- User-defined net scheduling
- Relative propagation delay
- Impedance constraints
- PCB Designers
You must have experience with or knowledge of one of the following tools:
Click here to view course learning maps, and here for complete course catalogs.