Home > Community > Forums > Custom IC SKILL > How to trigger VerilogA syntax checker and parser using SKILL?

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 How to trigger VerilogA syntax checker and parser using SKILL? 

Last post Thu, Jun 28 2012 10:15 AM by skillUser. 3 replies.
Started by Zhimiao Chen 28 Jun 2012 06:00 AM. Topic has 3 replies and 1958 views
Page 1 of 1 (4 items)
Sort Posts:
  • Thu, Jun 28 2012 6:00 AM

    How to trigger VerilogA syntax checker and parser using SKILL? Reply

     Hi, all,

     I am now wring a tool to generate VerilogA model, but failed to integrate it into the cadence environment with meaningful cell view. (that means: dbOpenCellViewByType(libName cellName "veriloga") == nil).The possible reason is that the generated veriloga code is not checked and parsed. Can cadence skill trigger a syntax checker and parser?

     

    Thanks!

    • Post Points: 20
  • Thu, Jun 28 2012 7:56 AM

    • skillUser
    • Top 10 Contributor
    • Joined on Fri, Sep 19 2008
    • Austin, TX
    • Posts 2,567
    • Points 15,575
    Re: How to trigger VerilogA syntax checker and parser using SKILL? Reply

    Hi,

    I think that you want to run the schInstallHDL() command on the Verilog syntax file to "install" it as a verilog view of a cell in a library.  Nothe that this is not the same as running Verilog In - the latter approach can be used to build schematics of the hierarchy described in the Verilog file, but the schInstallHDL method (I think) just does one level of hierarchy in the Verilog file.

    Hope this helps.

    Lawrence.

    • Post Points: 20
  • Thu, Jun 28 2012 10:13 AM

    Re: How to trigger VerilogA syntax checker and parser using SKILL? Reply

     Lawrence,

    That's for Verilog, not Verilog-A. 

    You probably need vmsUpdateCellViews(?lib "libName" ?cell "cellName" ?view "viewName")

    Andrew.

    • Post Points: 20
  • Thu, Jun 28 2012 10:15 AM

    • skillUser
    • Top 10 Contributor
    • Joined on Fri, Sep 19 2008
    • Austin, TX
    • Posts 2,567
    • Points 15,575
    Re: How to trigger VerilogA syntax checker and parser using SKILL? Reply

    Oops, sorry, I missed that it was VerilogA not Verilog.  Thanks for the correction Andrew!

    Lawrence.

    • Post Points: 5
Page 1 of 1 (4 items)
Sort Posts:
Started by Zhimiao Chen at 28 Jun 2012 06:00 AM. Topic has 3 replies.