White papers

Functional verification
Digital IC design
Custom IC design
Design for manufacturing
Silicon-package-board co-design

Functional verification	Top




Using a SoC Functional Verification Kit to Improve Productivity, Reduce Risk, and Increase Quality

Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success"

Reducing Block, Chip, and System Design Risk with a "Plan-to-Closure" Verification Approach

Front-End Logic Design: Taking the Risk out and Putting Schedule Predictability in

Accelerated Hardware/Software Co-verification - Speeds First Silicon and First Software

Assertion-based Acceleration

The e Language: A Fresh Separation of Concerns

Getting the Most Out of Formal Analysis

Components of a Complete Assertion-based Verification Solution

Spec-based verification: A new method for functional verification of Systems/ASICs

Design for Test Methodology—Case Study for Motorola C-5e DCP Using the Cadence Incisive Accelerator/Emulator

The Role of Design in Enhancing Nanometer Process Yield

ConvergenSC / Incisive Design Flow

Transaction-based co-simulation with Verisity Specman Elite

The Unified Verification Methodology

It's About Time: Requirements for the verification of Nanometer-scale Ics

The Case for a Simulation Server Farm

Reducing the Development Cycle for Third-Generation Wireless Communications Systems with Parallel Simulations (Course 542)

DSP SoC Design Methodology for Digital Cameras

Digital IC design	Top




Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation

Model-based Methods Critical for Effective Manufacturing-aware Physical Design

Next-Generation Signoff Analysis Tackles Electrical, Physical, And Manufacturing Challenges

Creating Low-Power Digital Integrated Circuits - The Implementation Phase

Architecting, Designing, Implementing, and Verifying Low-Power Digital Integrated Circuits

Complete Timing Signoff in the Nanometer Era

Design with Test

Front-End Logic Design: Taking the Risk out and Putting Schedule Predictability in

Cadence NanoRoute Ultra router for Linux on the IBM e-server

Accelerating Nanometer Yield Ramp with Yield Diagnostics

Empowering Design for Quality of Silicon

Clock Domain Crossing

NanometerTest—Methodology and Economics

Quality of Silicon—A Wired Way To Success

Routing Requirements for the Nanometer Era

Digital Custom Circuit RTL Model Development and Functional Verification

Global Synthesis for Timing Closure

Continuous Convergence: Meeting the Challenges of Today's Digital Designs

Signal Integrity Closure

Nanometer Sign-off – From Design to Manufacturing

Learning to Live with Electromigration

Physical Prototyping—the Key to Nanometer SoC Chip Design

Electromigration for Designers

Down to the Wire: Requirements for Nanometer Design Implementation

Designing Clock Signals—Predictability Counts

Noise-aware Timing Analysis

Closing the Nanometer Yield Chasm

Custom IC design	Top




Using Parasitic-Aware Simulation in the Design and Verification of Complex RF SiP Modules

Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation

AMD/Clear Shape: Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs

Virtuoso UltraSim Full-Chip Simulator Netlist-Based EMIR Flow

Specification-driven Design Environment is Key to Productivity Gains in Analog Design

Integrated Design Platform Addresses Growing Layout Closure Challenges

Virtuoso Multi-mode Simulation, a Complete Solution for Custom IC Designs

Adoption brief

Speeding Design of Custom Silicon

RF Design Methodology and Flow

AMS Top-level Flow

Analog Block Creation Flow with Reuse and Migration Flow

Analog-driven Physical Implementation Flow

Simulating Complex RF/Mixed-signal Designs Using Virtuoso UltraSim Full-chip Simulator

System/IC Reference Flow—The Advanced Custom Design Methodology

RF IC Reference Flow—The Advanced Custom Design Methodology

The Advanced Custom Design Methodology

AMSUltra: Virtuoso AMS Simulator With Virtuoso UltraSim FastSPICE Solver

TFT Design Verification With Virtuoso UltraSim Full-chip Simulator

FastSPICE Simulation In The Analog Design Environment

Spec-driven Design

The Analog/Mixed-Signal Reference Flow—Advanced Custom Design Methodology

Increasing Parametric Yield

The Advanced Custom Design Methodology

Reliability Simulation in Integrated Circuit Design

Using Hierarchy and Isomorphism to Accelerate Circuit Simulation

Transistor-Level Postlayout Simulation with Virtuoso UltraSIM Full-Chip Simulator

Behavior Modeling, Mixed-signal and RF Simulation with Spectre Circuit Simulator

On-Chip RF Isolation Techniques

It's About Time: Requirements for the verification of Nanometer-scale Ics

Rise of D/MS Semiconductors and Systems-on-a-Chip

Modeling and application of bonding pads

Receiver characterization using small-signal analysis

A user's guide to envelope following analysis

Extracting and using J-models to estimate ACPR in direct conversion transmitters

What the non-linear K-model does and how to make it do more

Extracting linear and non-linear K-models of RF receivers

Oscillator noise analysis in Spectre® RF

Using Pdisto effectively

RF IC package modeling

An introduction to the PLL library (version 4.4.5)

Periodic S-parameter and noise analysis using Spectre® RF PSP/PNOISE analyses

Behavioral modeling of RF circuits in Spectre RF (version 4.4.3 onwards)

Using the IPN function for RF simulations in the Affirma Analog Design Environment 4.4.5

Using the resolve optimizer with Spectre® RF in the Affirma Analog Design Environment

Substrate coupling analysis for RF and mixed-signal circuits (version 4.4.6)

Using tabulated S-parameters with Spectre RF

Analyzing time-varying noise properties with Spectre® RF

Modeling and simulation of jitter in PLL frequency synthesizers

Accurate Fourier Analysis for Circuit Simulators

Lumped Interconnect Models Via Gaussian Quadrature

Automated Layout of a Mixed-signal IC for a Laser Distance Measuring System

Functional Verification of a Differential Operation Amplifier

Noise-aware Timing Analysis

Closing the Nanometer Yield Chasm

Substrate Coupling Analysis in RF Circuits

Modeling and Simulation of On-Chip Spiral Inductors and Transformers

Design for manufacturing	Top




Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation

Model-based Methods Critical for Effective Manufacturing-aware Physical Design

Next-Generation Signoff Analysis Tackles Electrical, Physical, And Manufacturing Challenges

Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs

AMD/Clear Shape: Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs

The Role of Design in Enhancing Nanometer Process Yield

The Advanced Custom Design Methodology

On-Chip RF Isolation Techniques

Learning to Live with Electromigration

Electromigration for Designers

Power Grid Verification

Parasitic Extraction for Deep Submicron and Ultra-deep Submicron Designs

Silicon Validation of Full-chip Extraction

Noise-aware Timing Analysis

Closing the Nanometer Yield Chasm

Silicon-package-board co-design	Top




Using intelligent automation in advanced PCB design

Optimizing the PCB Design Chain and the Role of Library and Design-data Management

A New Paradigm in Logical Design Creation (Allegro Design Editor)

On Target, On Time—A Co-Design Methodology for System Interconnect

Return on Investment—A Co-Design Methodology for System Interconnect

Cadence Design Systems, Inc.