Cadence
Log In|Register|Resource Library|Worldwide
Asia-Pacific|China|EMEA|India|Israel|Japan|Korea|Taiwan|Global Office Locator

SolutionsProductsServicesSupport & Training Alliances Community About Cadence
Solutions: Design IP Mixed-Signal Low-Power Advanced Node Enterprise Verification Hosted Design System Development Suite Solutions Home
Products for: System Design and Verification Functional Verification Logic Design Digital Implementation Custom IC Design RF Design PCB Design IC Packaging and SiP Design Manufacturability Signoff More Products OrCAD Products Design IP Verification IP IP Catalog Products A-Z Products Home
Capabilities and Practices Methodology Services Design Services DFM Services Educational Services Programs SOI Design Hub Services Home
Support Support Offerings Support Process Cadence Online Support Software Downloads Computing Platform Support University Software Program Training Training Options Training Course Catalogs Support & Training Home
Programs and Initiatives System Realization Alliance Foundry Program IP Alliances ChipEstimate.com - Chip Planning Portal Connections Program Verification Alliance Program Channel Partner (VARs) Program Power Forward Initiative Standards and Languages PCB Service Bureaus Industry Memberships Alliances Home
Communities Industry Insights Blog Low Power Blog Mixed-Signal Design Blog System Design and Verification Cadence IP Blog Functional Verification Logic Design Digital Implementation Custom IC Design RF Design PCB Design IC Packaging and SiP Design Quicklinks All Blogs All Forums Community Search CDNLive! User Conferences Community Home
EDA Vision Visit the EDA360 microsite News and Events: Newsroom Events and Webinars Resources: Customer Success Newsletters Publications Multimedia Center Logos Company Info: Investor Relations Executive Team Careers Contact Us About Cadence Home

Blogs

  • What's Good About Allegro GRE 2 Point Flow? It’s in the ... By Gerald "Jerry" Grzenia
  • The Facts: Why Accelerated VIP Is Needed for SoC Verification By PeteHeller
  • How IP Subsystem Will Speed NVM Express (NVMe) Adoption By Richard Goering
  • In-Circuit Acceleration – A New IC Verification Use Model By Richard Goering
  • Adding Custom Shapes and Text is New and Improved in EDI System 11 By Brian Wallace
View all blogs »

Forums

  • System Design and Verification
  • Functional Verification   |   Functional Verification Shared Code
  • Logic Design
  • Digital Implementation
  • Custom IC Design   |   Custom IC SKILL
  • RF Design
  • PCB Design   |   PCB SKILL
  • IC Packaging and SiP Design
View all forums »

Follow Cadence

  • Cadence on Twitter   
  • Cadence on Facebook   
  • Cadence on YouTube   
  • RSS  



Join thousands of other users in the Cadence community!
Join now  |   Benefits of Membership

News

  • Cadence Introduces New NVM Express IP Solutions for Solid State Storage ... - May 15
  • Cadence Expands System and SoC Verification Offerings to Accelerate System ... - May 15
  • Netronome Reaps Significant Power, Performance and Area Benefits with Cadence ... - May 14
  • Fujitsu Semiconductor Adopts Cadence Chip Planning System for MCU Chips ... - May 8
View all news »

Events

  • Functional Verification Webinar Series 2012 -
    Mar 7 - Jun 27
  • CDNLive! EMEA 2012, Munich, Germany -
    May 14 - 16
  • Semico IMPACT Conference 2012, DoubleTree Hotel, San Jose, CA - May 16
  • Design Automation Conference (DAC) 2012, Moscone Center, San Francisco, CA - Jun 3 - 7
View all events »

Customer Success

  • Sigma Designs Adopts Cadence Simulation Acceleration Techniques
  • Zarlink Speeds Design Closure by 2x with Cadence Logic Synthesis Technology
  • Cadence Helps Casio Maintain its Lead in Digital Cameras
  • Silicon Laboratories Improves Verification Speed and Product Quality Using Incisive Enterprise...
View all success stories »

Resource Library

  • Hardware/Software Verification with Incisive Software Extensions- Technical Paper
  • Silicon Realization Enables Next-Generation IC Design White Paper- White Paper
  • Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success"- White Paper
  • Cadence DDR3/2 DRAM IP Solution- Datasheet
View Resource Library »

Popular Links

  • Newsroom   |   Blogs
  • Events and Webinars
  • Resource Library
  • Investor Relations
  • Cadence Online Support
  • Training
  • Products A to Z
About Cadence| Investor Relations| Careers| Terms of Use| Privacy Policy| US Trademarks| RSS Feeds
© Cadence Design Systems, Inc. All Rights Reserved.