Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions for:
Advanced Node
Enterprise Verification
Hosted Design
Low-Power
Mixed-Signal
System Development
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology and Technology Adoption
Design Collaboration
Talent Development
Programs
Startup Acceleration
VCAD
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Offerings
Training Course Catalogs
Support & Training Home
Programs and Initiatives
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
ASIC Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
News and Events
Newsroom
Multimedia Center
Events and Webinars
Company Info and Resources
Investor Relations
Executive Team
Cadence Research Laboratories
Community Involvement
Customer Success
Careers
Media Gallery
Contact Us
About Cadence Home
教育訓練
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Del.icio.us
Digg
Slashdot
Technorati
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
註 冊 管 理
課 程 目 錄
2009年 教育訓練課程
全部課程
|
新竹
|
台北
全部分類
Custom IC Design
Course Map
Q4-05
Skill Language Programming -v5.1.41
新竹
11/09 - 11/10
2天
截止
Q4-10
Virtuoso AMS Designer - v6.1.2
新竹
12/21 - 12/21
1天
我要報名
Q4-03
Virtuoso Chip Assembly Router - v11.2.41
新竹
11/16 - 11/17
2天
我要報名
Q4-07
Virtuoso Spectre RF - v5.1.41
新竹
11/23 - 11/24
2天
我要報名
Q4-08
Virtuoso UltraSim Full-Chip Simulator - v6.0
新竹
12/10 - 12/10
1天
我要報名
Q4-02
Virtuoso XL Layout Editor - v5.1.41
新竹
12/03 - 12/04
2天
我要報名
Digital IC design catalog
Course Map
Q4-36
Abstract Generator - v5.1.41
新竹
11/30 - 11/30
1天
我要報名
Q4-31
Clock Domain Crossing(CDC) Checking with Conformal - v6.1
新竹
12/08 - 12/08
1天
我要報名
Q4-32
EncounterRTL Compiler - v8.1
新竹
12/01 - 12/02
2天
我要報名
Q4-34
Floorplan Physical Synthesis Place & Route Flat- v8.1
新竹
11/18 - 11/20
3天
我要報名
Q4-30
Logic Equivalence Checking with Conformal - v8.1
新竹
12/07 - 12/07
1天
我要報名
Q4-37
SOC Encounter Advanced update-hierarchical & LP - v8.1 (lecture only;General SOCE experience is prerequisite)
新竹
11/11 - 11/11
1天
截止
Functional verification catalog
Course Map
Q4-42
Incisive Simulation (NC Verilog) - v6.2
新竹
12/23 - 12/24
2天
我要報名
Q4-45
Specman Elite Basics v6.1
新竹
12/14 - 12/15
2天
我要報名
Q4-41
Verilog Language and Application 6.2
新竹
11/25 - 11/27
3天
我要報名
Silicon-package-board co-design catalog
Course Map
Q4-52
Allegro Package Designer(APD) - v16
台北
11/25 - 11/26
2天
我要報名
Q4-50
Allegro PCB Editor SKILL Programming Language-(Internet learning free promotion course)
台北
11/11 - 11/12
2天
截止
Q4-53
SiP Digital Layout - v16
台北
11/25 - 11/27
3天
我要報名
Training Course Catalogs
Training Home
EMEA
India
North America
China
Japan
Korea
Taiwan
2009年第三季課程表已發佈
網絡系列課程(ILS) 在線學習
Esperan - 提供高質量培訓, 包括 VHDL, Verilog, and SystemC 等培訓
重要訊息
報名方式(注意事項/收費方式)
新竹上課地點
台北上課地點
聯絡益華