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SiP Layout v16.6

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
台北2013/11/22 - 11/221天09:30~17:3020人截止

課程種類Silicon-package-board co-design catalog; Silicon-package-board co-design catalog
產品版本v16.6
價格NT$5000 /per-day

課程種類:            符合製程的封裝設計與新版本功能進修

產品版本:            V16.6

 

這個課程介紹所有新版本的功能,讓原來已經在使用APD進一步了解SIP與最新的功能如何去操作與應用在目前的設計上,以加速整個設計流程,並達到設計的品質要求。

 

學習目標:

當課程結束後,你應該可以

·        完整的了解與操作APD/SIP最新版本每季更新的所有功能

·        得知新產品的相關資訊

 

使用的軟體:

·        Cadence SIP Layout XL, Allegro Package Router

 

軟體版本:

·        16.6 version

課程內容

Day 1

·        新功能的演練與講解

·        使用者自行操作熟悉新功能

·        新產品的介紹

 

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Course Description

The SiP Layout course covers a complete package design flow using the SiP Layout software. You begin by building components for your design, including the I/O component and die interfaces, using a variety of tools. You create standard and extended manufacturing constraints as well as high-speed electrical constraints. You will then use the wire-bonding toolset to wire bond the die to the package and route the package using both interactive and automatic routing techniques. You will create power and ground shapes, and then generate documentation and manufacturing files in both gerber and GDSII formats.

Learning Objectives

After completing this course, you will be able to:

  • Develop a process flow to suit your design needs
  • Create a cross section to model the SiP package
  • Use the SiP Layout physical and spacing constraint system to define physical and spacing constraints in your design
  • Define physical package I/O components in a variety of ways
  • Define the physical IC interface through different mechanisms
  • Create bond pads and blind/buried padstacks.
  • Wirebond a stacked die to the package.
  • Route the package interconnect manually and automatically.
  • Create power and ground shapes.
  • Run Assembly Rule Checks.
  • Generate documentation layers.
  • Create manufacturing data.

Software Used in This Course

  • Cadence® SiP Layout XL

Software Release(s)

  • SPB 16.6

Modules in this Online Course

  • Getting Started
  • Component Building
  • Design Setup
  • Wire Bonding
  • 3-D viewing
  • Routing
  • High Density Interconnect
  • Embedded Components
  • Manufacturing Output

Audience

  • This course is for SiP designers and design engineers.

Prerequisites

You must have experience with or knowledge of the following:

  • You need a working knowledge of single or multichip design and construction.

System Requirements for Online Courses

  • Cadence software as listed above installed and licensed

Related Courses

  • SiP RF Architect

Click here to view course learning maps, and here for complete course catalogs.


相關課程

 Allegro High-Speed Constraint Management v16.6
 Allegro Package Designer v16.6