Incisive Comprehensive Coverage with IMC v12.2
|新竹||2013/12/03 - 12/03||1天||09:30~17:30||30人||截止|
|課程種類||Functional verification catalog; Functional verification catalog|
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Incisive® comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog®, and mixed-language designs. Not all coverage features are available with all languages. The course uses the Incisive® Metrics Center for reporting and analysis.
The course discusses the collection and analysis of the following types of coverage:
- Code (block, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog covergroups
- Control-oriented functional coverage using PSL and SystemVerilog assertions
After completing this course you will be able to:
- Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs
Software Used in This Course
- Incisive Enterprise Simulator - XL
Modules in this Online Course
This training consists of one module, which includes:
- Coverage Introduction
- Scoring code coverage with the integrated Incisive comprehensive coverage
- Scoring functional coverage using SystemVerilog covergroups and PSL and SystemVerilog assertions
You must have:
- Familiarity with the SystemC, VHDL, or Verilog languages, and with design and design verification.
- Familiarity with SystemVerilog covergroups and SystemVerilog and PSL assertions. This course reviews them only briefly.
System Requirements for Online Courses
- Cadence software as listed above installed and licensed
- SystemC Language Fundamentals
- VHDL Language and Application
- Verilog Language and Application
- SystemVerilog Language and Application
- Incisive SystemC, VHDL, and Verilog Simulation
Click here to view course learning maps, and here for complete course catalogs.
相關課程 Verilog Language and Application 9.2 System Verilog Language and Application - v9.2 Incisive Simulation (NC Verilog) v11.1