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Encounter Digital Implementation (Flat) - v13.1

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/12/10 - 12/123天09:30~17:3030人截止

課程種類Digital IC design catalog; Digital IC design catalog
產品版本v13.1
價格NT$5000/per-day

Course Description

In this course, you explore high-level design planning and implementation by using the Encounter® Digital Implementation software. You learn several techniques for floorplanning and placement while implementing timing closure strategies. You run the detail router to route a design, fix routing violations, and use timing and signal integrity options. You will explore challenges and solutions for 20nm design implementation.

Other topics in this course include extracting parasitics, creating clock trees, running delay calculation, and using database access commands. You also explore wire editing, metal fill, ECO, and physical verification.

This course was formerly called Floorplanning, Physical Synthesis, Place and Route (Flat).

Learning Objectives

After completing this course, you will be able to:

  • Floorplan a design
  • Place blocks and standard cells
  • Run scan optimization
  • Run Trial Route and route the power
  • Estimate parasitics and generate timing information
  • Analyze routing congestion
  • Create clock trees
  • Run power analysis
  • Modify net attributes
  • Edit wires manually
  • Route with signal integrity options
  • Extract RC data
  • Optimize and close timing
  • Fix routing violations
  • Route in ECO mode
  • Address 20nm design challenges
  • Run database access commands
  • Run foundation flow scripts

Software Used in This Course

  • Encounter Digital Implementation System XL

Software Release(s)

  • EDI131

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Floorplanning the design
  • Planning power
  • Routing power
  • Placing cells and blocks
  • Optimizing and reordering scan chains
  • Analyzing route feasibility using Trial Route

Day 2

  • Extracting parasitics and analyzing timing
  • Running optimization and closing timing
  • Implementing the clock tree
  • Analyzing power

Day 3

  • Selecting routing attributes and options
  • Performing wire editing and metal fill
  • Running signal integrity
  • Running database access commands
  • Implementing an engineering change order
  • Writing out a design
  • Creating and running Foundation Flow scripts

Audience

  • CAD Engineers
  • Chip Designers
  • Physical Layout Designers

Prerequisites

You must have experience with or knowledge of:

  • Design methodology
  • Place and Route

Related Courses

  • Encounter RTL Compiler
  • Encounter Digital Implementation (Hierarchical)
  • Logic Equivalence Checking with Encounter Conformal EC
  • Low Power Implementation

Click here to view course learning maps, and here for complete course catalogs.

Special Note

This course does not include RTL synthesis. For detailed knowledge of running RTL synthesis, take the Encounter® RTL Compiler course.

相關課程

 EncounterRTL Compiler - v12.1
 Encounter Digital Implementation (Hierarchical) v13.2
 Logic Equivalence Checking with Encounter Conformal EC - v12.1
 Low-Power Verification with Encounter Conformal v12.1