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Low-Power Verification with Encounter Conformal v12.1

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課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/11/22 - 11/221天09:30~17:3030人截止

課程種類Digital IC design catalog; Functional verification catalog
產品版本v12.1
價格NT$5000/per-day

Course Description

In this course, you learn to verify low-power designs using Encounter® Conformal® Low Power. In the labs, you debug practical examples of common power format (CPF) violations, functional and structural violations, and nonequivalences.

Learning Objectives

After completing this course, you will be able to:

  • Identify Encounter® Conformal® low-power features
  • Use power intent architect (PIA) to create power intent
  • Run library verification checks to prepare libraries with power intent
  • Apply low-power checks on a RTL with power intent
  • Apply low-power checks on gate netlist with power intent
  • Run low-power equivalency checks between gate netlist and RTL using the power intent
  • Apply low-power checks on a physical netlist with power intent
  • Run low-power equivalence checking between the physical and gate-level netlists
  • Run transistor level checks on a physical netlist

Software Used in This Course

  • Encounter Conformal Low Power

Software Release(s)

  • CONFRML121

Course Agenda

Day 1

  • Overview
  • Using Power Intent Architect (PIA)
  • Labs - Running Power Intent Architect (PIA)
  • Labs - Create IO Pads using PIA
  • Library Preparation
  • Lab - Library Verification Flow
  • Logical Verification
  • Lab - Running Conformal Low-Power on a Logical Netlist
  • Synthesis Verification
  • Lab - Running Low-Power Checks Before Synthesis
  • Lab - Running Low-Power Checks After Synthesis
  • Lab - Running Equivalence Checks on the Synthesized Netlist against the RTL
  • Physical Verification
  • Lab - Running Low-Power Checks on a Physical Netlist
  • Lab - Running Equivalence Check on the Physical Netlist against the Synthesized Netlist
  • Using CLP Successfully
  • Transistor level checks

Audience

  • ASIC Designers

  • Design Engineers
  • Digital IC Designers
  • FPGA Designers
  • Hardware Engineers
  • Logic Designers
  • Verification Engineers

Prerequisites

You must have experience with or have knowledge of the following:

  • Design methodology
  • Logic Design
  • HDL
  • Encounter Conformal XL

Or you must have completed the following courses:

  • Logic Equivalence Checking with Encounter Conformal EC

Related Courses

  • Logic Equivalence Checking with Encounter Conformal EC

Click here to view course learning maps, and here for complete course catalogs.

相關課程

 Logic Equivalence Checking with Encounter Conformal EC - v12.1