EncounterRTL Compiler - v12.1
|新竹||2013/12/17 - 12/18||2天||09:30~17:30||30人||截止|
|課程種類||Digital IC design catalog|
In this course, you explore the features of the Cadence® Encounter® RTL Compiler with global synthesis technology. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, optimize for low power, and interface with other tools.
After completing this course, you will be able to:
- Apply the recommended global synthesis flow using Encounter RTL Compiler.
- Navigate the design database and manipulate design objects.
- Constrain designs for global synthesis and run static timing analysis.
- Optimize RTL designs for timing and area using several strategies.
- Diagnose and analyze synthesis results.
- Use the extended datapath features of the compiler.
- Analyze and synthesize the design for low-power.
- Optimize designs using the physical synthesis flow.
- Interface with other tools and place-and-route flows.
Software Used in This Course
- Encounter RTL Compiler with physical
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
- About this Course
- Introduction to Encounter RTL Compiler
- HDL Modeling
- Synthesis Flow
- Datapath Synthesis
- Optimization Strategies
- Low-Power Synthesis
- Interface to Other Tools
- Physical Synthesis
- Test Synthesis
- ASIC Designers
- Digital IC Designers
- Logic Designers
You must have experience with or knowledge of the following:
- Any HDL such as Verilog® (recommended) or VHDL
- Static Timing Analysis
Or you must have completed the following courses:
- Basic Static Timing Analysis
- Verilog Language and Application
- Logic Equivalence Checking with Encounter Conformal EC
- Floorplanning, Physical Synthesis, Place and Route (Flat)
Click here to view course learning maps, and here for complete course catalogs.
相關課程 Logic Equivalence Checking with Encounter Conformal EC - v12.1 Encounter Digital Implementation (Flat) - v13.1