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EncounterRTL Compiler - v12.1

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/12/17 - 12/182天09:30~17:3030人截止

課程種類Digital IC design catalog
產品版本12.1
價格NT$5000/per-day
Course Description

In this course, you explore the features of the Cadence® Encounter® RTL Compiler with global synthesis technology. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, optimize for low power, and interface with other tools.

Learning Objectives

After completing this course, you will be able to:

  • Apply the recommended global synthesis flow using Encounter RTL Compiler.
  • Navigate the design database and manipulate design objects.
  • Constrain designs for global synthesis and run static timing analysis.
  • Optimize RTL designs for timing and area using several strategies.
  • Diagnose and analyze synthesis results.
  • Use the extended datapath features of the compiler.
  • Analyze and synthesize the design for low-power.
  • Optimize designs using the physical synthesis flow.
  • Interface with other tools and place-and-route flows.

Software Used in This Course

  • Encounter RTL Compiler with physical

Software Release(s)

  • RC121

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Section 1

  • About this Course
  • Introduction to Encounter RTL Compiler
  • HDL Modeling
  • Synthesis Flow
  • Datapath Synthesis
  • Optimization Strategies

Section 2

  • Low-Power Synthesis
  • Interface to Other Tools
  • Physical Synthesis
  • Test Synthesis

Audience

  • ASIC Designers
  • Digital IC Designers
  • Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Any HDL such as Verilog® (recommended) or VHDL
  • Static Timing Analysis

Or you must have completed the following courses:

  • Basic Static Timing Analysis
  • Verilog Language and Application

Related Courses

  • Logic Equivalence Checking with Encounter Conformal EC
  • Floorplanning, Physical Synthesis, Place and Route (Flat)

Click here to view course learning maps, and here for complete course catalogs.

相關課程

 Logic Equivalence Checking with Encounter Conformal EC - v12.1
 Encounter Digital Implementation (Flat) - v13.1