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Encounter Conformal Constraint Designer (SDC/CDC Checks) - v12.1

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課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/12/19 - 12/191天09:30~17:3030人截止

課程種類Digital IC design catalog; Digital IC design catalog
產品版本v12.1
價格NT$5000/per-day

Course Description

In this course, you use Encounter® Conformal® Constraint Designer to manage constraints for complex system-on-a-chip designs from RTL through layout. To avoid poorly written or mismatched constraints that result in bad silicon, you validate the constraints by checking the structure, syntax, and implementation.

During chip integration, constraints might conflict in terms of clock definition, input and output delay settings, and exceptions. You learn to detect these errors earlier in the design cycle by using hierarchical constraint checks. You also automatically generate and validate false path exceptions from critical paths by applying functional validation.

Learning Objectives

After completing this course, you will be able to:

  • Identify the flow of the constraint design and verification
  • Create SDCs using template generation and using SDC Advisor
  • Debug SDC lint
  • Debug structural and other SDC violations using the Helix Rule Manager
  • Analyze clock domain crossing issues

Software Used in This Course

  • Encounter Conformal Constraint Designer - XL

Software Release(s)

  • CONFRML121

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Introduction to the Constraint Designer Software
  • Constraint Verification Flow
  • Lab: Quick Overview
  • SDC Template Generation
  • Lab: Run SDC Template Generation
  • Lab: Using SDC Advisor
  • SDC Lint Checks
  • Lab: Run SDC Lint Checks
  • SDC Policy Checks
  • Lab: Using Helix Rule Manager
  • Clock Domain Crossing
  • Lab: Run Clock Domain Crossing Checks
  • Lab: Run Convergence Checks
  • Lab: Run Set-Reset Checks
  • SDC Integration and Comparison

Audience

Verification Engineers

Design Engineers

Place and Route Designers

ASIC Designers

Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Static Timing Analysis
  • Standard Design Constraints (SDC)

Or you must have completed the following courses:

  • Basic Static Timing Analysis

Related Courses

  • Encounter RTL Compiler
  • Logic Equivalence Checking with Encounter Conformal EC

Click here to view course learning maps, and here for complete course catalogs.

相關課程

 EncounterRTL Compiler - v12.1
 Logic Equivalence Checking with Encounter Conformal EC - v12.1