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Assura DRC/ LVS Rules Writer - v3.1.4

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/12/04 - 12/052天09:30~17:3030人截止

課程種類Design for manufacturing catalog; Design for manufacturing catalog
產品版本v3.1.4
價格NT$5000/per-day

Assura Rules Writer v3.1.4

Delivery Method: Instructor-Led

Item Description

The Assura™ Rules Writer course provides complete application instruction for all aspects of verification. The techniques covered are applicable to all technologies and process types:

  • CMOS
  • Bipolar
  • High/low voltage
  • Memory
  • Analog/mixed signal
  • ASIC

Learning Objectives

In this course you will:
  • Learn how to write rules for Assura physical verification
  • Learn how to optimize your rules

Software

Virtuoso® Layout Editor v5.1.41
Assura™ Physical Verification v3.1.4

Audience

  • CAD Engineers
  • Design Kit Specialists
  • Layout Designers with CAD background

Special Notes

Optimization and performance techniques are embedded in each respective application section.

Prerequisites

The student must have experience with the execution and error resolution of some type of verification tool.

Although not required, exposure to the items listed below will provide the student with a better learning experience.

  • Semiconductor process background
  • Physical design experience
  • SKILL programming experience

Related Courses

Assura RCX Developer