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Virtuoso AMS Designer v11.1

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/12/20 - 12/201天09:30~17:3030人截止

課程種類Custom IC Design; Custom IC Design
產品版本v11.1
價格NT$5000 /per-day
Virtuoso AMS Designer v11.1

Category: Analog Mixed Signal, Design Verification, Mixed-Signal Simulation

Course Description

In the Virtuoso® Analog Mixed-Signal (AMS) Designer course, you use the mixed-signal, mixed-language Virtuoso AMS Simulator. You use two different simulation models: the Virtuoso Analog Design Environment graphical-interface model and the command-line control-based model using the IRUN executable. You learn about the concept of discipline resolution and insertion of connect modules. You use the Hierarchy Editor to create design configurations. In addition to the Virtuoso Visualization and Analysis XL waveform viewer, you use the SimVision tool to debug simulations. You use the AMS simulator with the UltraSim solver. You are introduced to behavioral modeling using the Verilog®-AMS mixed-signal modeling language. You learn the Incisive® mixed-signal verification flow and Verilog testbench reuse with information on the SystemVerilog language, the SystemC language, the Common Power Format (CPF), the MATLAB language, and the Simulink coder.

Learning Objectives

After completing this course, you will be able to:

  • Run Virtuoso Analog Mixed-Signal (AMS) Designer through typical simulations using command-line control and the Virtuoso Analog Design Environment
  • Switch between two analog solvers, the Virtuoso Spectre® Circuit Simulator and the Virtuoso UltraSim Full-chip Simulator, to optimize simulation speed and accuracy
  • Create configurations to allow easy replacement of behavioral models with more detailed schematic designs
  • Create simple models with the Verilog-AMS modeling language
  • Understand mixed-signal discipline resolution, apply signal disciplines and control connect module placement
  • Use the wreal data type for real-valued modeling
  • Reuse Verilog testbenches for mixed-signal designs
  • Understand verification flows using SystemVerilog and SystemC

Software Used in This Course

  • AMS Designer Simulator in Incisive 11.1 and Virtuoso IC 6.1.5

Software Release(s)

  • INCISIV 11.1, IC 6.1.5

Course Sessions (Sessions will be adjusted upon local needs.)

Session 1

  • Getting Started
  • Core Topics of Virtuoso AMS Designer (combined track)
  • Creating Configurations with the Hierarchy Editor (analog track)

Session 2

  • Introduction to Virtuoso AMS Designer in ADE (analog track)
  • Connect Modules (combined track)
  • Using the UltraSim Solver in AMS (analog track)

Session 3

  • Using SimVision to Debug Simulations (digital track)
  • Basics of Verilog-AMS Modeling (digital track) (Optional)

Session 4

  • Using the AMS Incisive Flow for Design Verification (digital track)
  • AMS Verification Capabilities (digital track)
  • If needed, there are optional modules or appendixes, including software licensing.

Audience

  • Analog/Mixed-Signal IC Designers
  • Analog/Mixed-Signal Verification Engineers
  • Custom Circuit Designers
  • System-level IC Designers

Prerequisites

You must have experience with or already have knowledge of the following:

  • UNIX or Linux OS

You must have completed the following courses:

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