Home > Cadence Taiwan > Training > 教育訓練

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Analog Modeling with Verilog-A v13.1

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/11/29 - 11/291天09:30~17:3030人截止

課程種類Custom IC Design; Custom IC Design
產品版本v13.1
價格NT$5000 /per-day

Course ID: ES_82086IA_MMSIM13.1

Course Description

In this course, you use the Virtuoso® Analog Design Environment and Virtuoso Spectre® Circuit Simulator to simulate analog circuits with Verilog-A models. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. You use the Verilog-A syntax, structure Verilog-A modules, and generate symbols for your Verilog-A cells for use in a system hierarchy. You also learn to format output data and to use waveform filters to improve simulation performance. In this course, you also examine the AHDL Linter feature to detect potential bugs in the Verilog-A codes.

Learning Objectives

After completing this course, you will be able to:

  • Determine the importance of top-down design methodology for accelerating complex system development
  • Write behavioral models of electrical circuits using the correct Verilog-A language and syntax
  • Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso Analog Design Environment and the command line
  • Verify that Verilog-A modules properly describe the intended function
  • Use software design tools to facilitate model development

Software Used in This Course

  • Virtuoso Analog Design Environment L
  • Virtuoso Spectre Circuit Simulator
  • Virtuoso Visualization and Analysis XL

Software Release(s)

  • IC 6.1.6, MMSIM 13.1

Modules in this Online Course

  • About This Course and Getting Help
  • Basic Modeling Concepts
  • Verilog-A Flow and Simulation
  • The Design of Verilog-A Modules
  • Verilog-A Modeling Descriptions
  • Analog Event Detection
  • Analog Operators and Filters
  • Verilog-A Functions and Operators
  • Looping and Conditional Constructs
  • User-Defined and System Functions
  • Displaying and Printing Results
  • AHDL Linter Checks

Audience

  • Analog/Mixed-Signal Designers
  • IC Designers
  • Library Developers
  • System-level IC Designers

Prerequisites

You must have experience with or already have knowledge of the following:

  • Some programming, UNIX or Linux, a text editor

You must have completed the following courses:

You must have experience with the following software:

  • Virtuoso Analog Design Environment L
  • Virtuoso Spectre Circuit Simulator
  • Virtuoso Visualization and Analysis XL

System Requirements for Online Courses

  • For system requirements, click here
  • Cadence software as listed above, installed and licensed

Related Courses

Click here to view course learning maps, and here for complete course catalogs.

相關課程

 Virtuoso AMS Designer v11.1