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Encounter Conformal Constraint Designer (SDC/CDC Checks) - v10.1

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/9/26 - 9/261天09:30~17:3020人截止

課程種類Digital IC design catalog; Digital IC design catalog
產品版本v10.1
價格NT$5000 /per-day

Encounter Conformal Constraint Designer v10.1

Category: Logical Equivalency Checker

Course Description

In this course, you use Encounter® Conformal® Constraint Designer to manage constraints for complex system-on-a-chip designs from RTL through layout. To avoid poorly written or mismatched constraints that result in bad silicon, you validate the constraints by checking the structure, syntax, and implementation.

During chip integration, constraints might conflict in terms of clock definition, input and output delay settings, and exceptions. You learn to detect these errors earlier in the design cycle by using hierarchical constraint checks. You also automatically generate and validate false path exceptions from critical paths by applying functional validation.

Learning Objectives

After completing this course, you will be able to:

  • Identify the flow of the constraint design and verification
  • Create SDCs using template generation and using SDC Advisor
  • Debug SDC lint
  • Debug structural and other SDC violations using the Helix Rule Manager
  • Analyze clock domain crossing issues

Software Used in This Course

  • Encounter Conformal Constraint Designer - XL

Software Release(s)

  • CCD101

Course Sessions (Sessions will be adjusted in local classroom)

Session 1

  • Introduction
  • CCD Flow
  • Quick Overview
  • SDC Generation
  • Run SDC Template generation
  • Using SDC Advisor
  • SDC Lint Checks
  • Run SDC Lint Checks

Session 2

  • SDC Policy Checks
  • Using Helix Rule Manager
  • Clock Domain Crossing
  • Run clock domain crossing checks
  • Run convergence checks
  • Run set-reset checks

Prerequisites

You must have experience with or knowledge of the following:

  • Static Timing Analysis
  • Standard Design Constraints (SDC)

Or you must have completed the following courses:


相關課程

 Encounter RTL Compiler v11.1
 Logic Equivalence Checking with Conformal v11.1