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Logic Equivalence Checking with Conformal v11.1

返回課程目錄
課程安排
上課地點課程起訖日課程天數上課時間限制人數報名狀態
新竹2013/7/18 - 7/181天09:30~17:3020人截止

課程種類Digital IC design catalog
產品版本v11.1
價格NT$5000 /per-day
Logic Equivalence Checking with Encounter Conformal EC v11.1

Category: Formal Verification, Logical Equivalency Checker

Course Description

In this course, you use the Encounter® Conformal® Equivalence Checker to perform functional verification. You learn the basic flow of equivalence checking and how to run hierarchical comparison of designs. The lab exercises follow major topics and are designed to be directly applicable in design and design verification. After completing this course, you will be able to set up and verify your designs, analyze the results, and debug failing results.

Learning Objectives

After completing this course, you will be able to:

  • Use Encounter Conformal logic equivalence checking for flat and hierarchical design comparison
  • Read libraries and designs
  • Apply design constraints and modeling directives
  • Apply the mapping process and debug unmapped key points
  • Apply the compare process and debug non-equivalent points
  • Run and debug a hierarchical design comparison
  • Run the debugging of the setup of a design
  • Run the debugging of the mapping of a design
  • Analyze and fix the nonequivalences of a design
  • Analyze and fix the aborts in a design

Software Used in This Course

  • Encounter Conformal XL

Software Release(s)

  • CONFRML101

Course Sessions

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Session 1

  • Introduction to the Encounter Conformal product family
  • Introduction to logic equivalence checking
  • Running Encounter Conformal Equivalence Checker in setup mode
  • Specifying blackboxes
  • Reading library and design files
  • Applying design constraints
  • Specifying modeling directive

Session 2

  • Running Encounter Conformal Equivalence Checker in LEC mode

    • Applying the mapping process
    • Resolving unmapped key points
    • Running a comparison
    • Debugging nonequivalent key points
  • Comparing hierarchical designs

Session 3

  • Debugging Setup Issues
  • Debugging Mapping Issues

Session 3

  • Debugging Nonequivalences
  • Debugging Aborts

Audience

  • ASIC Designers
  • Design Engineers
  • Digital IC Designers
  • FPGA Designers
  • Hardware Engineers
  • IC Designers
  • Logic Designers
  • Place and Route Designers
  • Verification Engineers

Prerequisites

You must have experience with or knowledge of:

  • HDL
  • Logic Design

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