In current high speed digital system design, power integrity is the key for system performance. Try to stay low impedance for power/ground system can help to reduce power/ground and signal current loop that helps to improve signal quality. Through 3 days course training, user can learn basic EM concept and advanced SI/PI analysis skill with Cadence/Sigrity solutions.
Day1: [Sigrity] Power Integrity Analysis - From DC to AC
Day2: [Sigrity] Power Aware Signal Integrity Analysis Part-I: For DDRx Analysis
Day3: [Sigrity] Power Aware Signal Integrity Analysis Part-II: For Serdes Analysis
【Agenda】
Day 1: Power Integrity Analysis - From DC to AC
(1) The importance of power integrity
(2) DC IR drop analysis with PowerDC
(3) Voltage sense line optimization for switching power supply
(4) Multi-board IR drop analysis
(5) Electrical and thermal co-simulation and thermal model extraction
(6) Input and transfer impedance introduction for AC analysis
(7) Inductance and capacitance extraction from power/ground system
(8) Decaps optimization with OptimizePI
Day 2: Power Aware Signal Integrity Analysis Part-I: For DDRx analysis
(1) Introduction to S-parameter, passivity and causality
(2) Signal integrity with power aware
(3) Model extraction with PowerSI
(4) Timing problem for source synchronous system
(5) DDRx analysis with SystemSI-PBA
Day 3: Power Aware Signal Integrity Analysis Part-II: For Serdes analysis
(1) Brief introduction to 3DFEM
(2) Setup for 3DFEM analysis
(3) S-parameter extraction on differential vias
(4) Impulse response for channel simulation
(5) Channel simulation with SystemSI-SLA (include AMI model)